The stress analysis and parametric studies for the low-k layers of a chip in the flip-chip process

Abstract

Using low-k/ultralow-k (LK/ULK) materials as the inter-layer dielectrics (ILD) and inter-metal dielectrics (IMD) in copper connections were implemented to meet the electrical performance requirements in the advanced chips. ULK materials are fragile and the mechanical failures in ULK materials are critical during chip packaging processes, such as the solder reflow in the flip-chip. A crack or delamination that initiates within the high thermo-mechanical stress regions can propagate into the active area of the chip in packaging, which involves the chip-packaging interaction (CPI) problem. In this study, we proposed a three-dimensional sub-modeling finite element approach considering an effective layer for the back end of line (BEOL) microstructures in the global model to improve the accuracy. The approach surmounted the difficulty of the large size difference between the chip and the ULK layers in computations. The stress analysis and parametric studies for a designed ULK chip with 40nm technical node under the flip-chip reflow was performed based on the present method. The effects of the selected parameters were ranked and the optimal combination of the factors was achieved.