(Invited, Digital Presentation) Advanced Methodology for Assessing Chip Package Interaction Induced Stress Effects on Chip Performance and Reliability

Abstract

In IC industry, the use of multiple die stack packaging has emerged to meet the increasing demand in miniaturization and improved functionality of mobile devices. During chip operation, transistor power dissipation raises temperature unevenly across a die. The generated thermal hotspots negatively impact reliability and degrade performance. In mechanical aspects, dies become thinner, and bumps and pitch become smaller, which makes heat dissipation more difficult, and lead to increase in mechanical stress. Such stress may cause carrier mobility degradation for transistors and could lead to parametric circuit failure. In the back-end-of-line (BEoL) interconnects, the employed ultra-low k materials prone to damage interconnects when mechanical stress is present, due to its brittle nature and poor adhesion to the barrier materials. These stresses originated at the die packaging step due to thermal mismatch between die and package materials, which is termed as chip package interaction (CPI). We call mechanical CPI (mCPI) when such stress affects reliability of the whole chip, i.e., BEoL, RDL (redistribution layer), bump, or TSVs (through silicon vias). When such stress affects device performance, we call electrical CPI (eCPI).To analyze CPI effects on a feature scale, i.e., in transistor channel or in the individual metal line or ILD (inter layer dielectric) /IMD (inter metal dielectric) gap, an analysis tool must generate accurate feature-scale stress variation across a die. Finite element analysis (FEA) is widely used for analyzing CPI induced problems. However, the traditional FEA cannot effectively handle feature-scale geometries due to huge memory consumption, and instead, treats a die as a uniform material block. Therefore, this approach cannot describe stress distribution caused by local non-uniformity of metal line distribution and fail to provide the needed accuracy for feature-scale analysis. [1]Here, we present an advanced physics-based EDA tool that overcomes the above-mentioned problems by introducing the novel methodology of extracting effective anisotropic thermal-mechanical properties (EMP), as well as employing FEA-based multi-scale simulation procedure. Prior to running FEA, the tool extracts EMP that accurately represent non-uniformities at different scales within a simulation domain. Here, each metal layer in a die is considered a binary system that consists of metal inclusions embedded in an insulator matrix. By dividing the die area into bins, metal density dependent effective properties for each bin are calculated according to theory of anisotropic composite materials. Anisotropy of properties can be obtained by taking routing direction of metal lines into account [2, 3]. EMP can adjust to multi-scale by varying bin size as shown in Fig.1. Here, Young’s modulus is extracted globally with coarse grid, and on sub-modeling region with very fine grid, which shows the corresponding property variation with much finer scale. Since EMP constructs no actual geometrical objects, the methodology can efficiently handle feature-scale objects on a large layout region. When a user selects a circuit block, or a region to be analyzed in detail, the automated tool flow enables two step stress simulation procedure, which is schematically shown in Fig. 2. First, the global-scale stress simulation is performed with coarse both the simulation mesh and EMP bin and extracts the boundary displacements for the circuit block. These boundary displacements are employed in the sub-modeling, with employed fine mesh and EMP bin.Figure 3 demonstrates the importance of EMP for accurate resolution of stress field. The 2D color maps show the x-component of stress distributions in a circuit block as a result of sub-modeling. Here, die BEoL is represented by EMP in (a), while in (b), the entire die including BEoL is represented by silicon, which is employed in traditional FEA. The stress pattern due to interconnect layout details are visible only when EMP is employed. The difference is even more pronounced when 1D stress profile is compared.By back annotating the obtained stress components in a SPICE netlist, the tool enables a user to perform accurate circuit simulation with accounted CPI effects. In eCPI analysis, the tool has been validated by employing measurements of different types of devices [4].The additional tool capabilities that will be presented are mCPI analysis and thermomechanical stress analysis during chip operating conditions.[1] R. Radojcic, More-than-Moore 2.5D and 3D SiP Integration, Springer, 2017.[2] V. Sukharev et al. J. Electron Test, vol. 28, pp. 63-72, 2012[3] V. Sukharev et al., Proc. Int. 3D Systems Integration Conference, 2019[4]. A. Kteyan, et al. Proc. ISPD 2022 Figure 1