Interfacial Oxide Layer Research Articles

Comparative study on nitridation and oxidation plasma interface treatment for AlGaN/GaN MIS-HEMTs with AlN gate dielectric

This paper demonstrated the comparative study on interface engineering of AlN/AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) by using plasma interface pre-treatment in various ambient gases. The 15 nm AlN gate dielectric grown by plasma-enhanced atomic layer deposition significantly suppressed the gate leakage current by about two orders of magnitude and increased the peak field-effect mobility by more than 50%. NH3/N2 nitridation plasma treatment (NPT) was used to remove the 3 nm poor-quality interfacial oxide layer and N2O/N2 oxidation plasma treatment (OPT) to improve the quality of interfacial layer, both resulting in improved dielectric/barrier interface quality, positive threshold voltage (Vth) shift larger than 0.9 V, and negligible dispersion. In comparison, however, NPT led to further decrease in interface charges by 3.38 × 1012 cm−2 and an extra positive Vth shift of 1.3 V. Analysis with fat field-effect transistors showed that NPT resulted in better sub-threshold characteristics and transconductance linearity for MIS-HEMTs compared with OPT. The comparative study suggested that direct removing the poor interfacial oxide layer by nitridation plasma was superior to improving the quality of interfacial layer by oxidation plasma for the interface engineering of GaN-based MIS-HEMTs.

Influence of Oxide Interlayer by TiN Metal Gate in High-k First CMOS Devices

Due to its good film stability and electric property of high effective work function, TiN film has been widely used as high-k gate dielectric capping layer or work function metal in advanced High-k/metal gate CMOS devices. In this work, different TiN films were prepared by atomic layer deposition (ALD) and plasma vapor deposition (PVD) respectively, their thermal stability and interaction with gate stack films were investigated. Furthermore, their impacts on interface properties of interfacial oxide/high-k and interfacial oxide/silicon were also studied. The results show that both ALD and PVD TiN films have good thermal stability, while they tend to gather oxygen from atmosphere during sequential process steps. After high temperature annealing, the gathered oxygen in TiN film is easy to diffuse upward into TiN/poly-Si interface to form a thin TiSixOy layer above TiN film, and diffuse downward through high-k dielectric film resulting in interfacial oxide layer (IL) regrowth.

Efficient organic photovoltaic cells on a single layer graphene transparent conductive electrode using MoOx as an interfacial layer.

The large surface roughness, low work function and high cost of transparent electrodes using multilayer graphene films can limit their application in organic photovoltaic (OPV) cells. Here, we develop single layer graphene (SLG) films as transparent anodes for OPV cells that contain light-absorbing layers comprised of the evaporable molecular organic semiconductor materials, zinc phthalocyanine (ZnPc)/fullerene (C60), as well as a molybdenum oxide (MoOx) interfacial layer. In addition to an increase in the optical transmittance, the SLG anodes had a significant decrease in surface roughness compared to two and four layer graphene (TLG and FLG) anodes fabricated by multiple transfer and stacking of SLGs. Importantly, the introduction of a MoOx interfacial layer not only reduced the energy barrier between the graphene anode and the active layer, but also decreased the resistance of the SLG by nearly ten times. The OPV cells with the structure of polyethylene terephthalate/SLG/MoOx/CuI/ZnPc/C60/bathocuproine/Al were flexible, and had a power conversion efficiency of up to 0.84%, which was only 17.6% lower than the devices with an equivalent structure but prepared on commercial indium tin oxide anodes. Furthermore, the devices with the SLG anode were 50% and 86.7% higher in efficiency than the cells with the TLG and FLG anodes. These results show the potential of SLG electrodes for flexible and wearable OPV cells as well as other organic optoelectronic devices.

Effect of Grit Blasting Treatment for Forming Interfacial Oxide Layer in Thermal Barrier Coating

Effect of Grit Blasting Treatment for Forming Interfacial Oxide Layer in Thermal Barrier Coating

Characterization of spin-coated gallium oxide films and application as surface passivation layer on silicon

Gallium oxide films have shown a great potential as passivation layers on silicon solar cells. In this work, we employed the spin-coating method to form gallium oxide films on p-type silicon substrate as a surface passivation layer. The dependences of the structure and the surface passivation effect of the gallium oxide films on the annealing temperatures were investigated. Both Ga 3d and 2p 3/2 regions were also measured by X-ray photoelectron spectroscopy analysis to obtain the complementary information on the composition of the Ga2O3 films (versus depth). In addition, the Qeff polarity change and a C-V clockwise hysteresis of Ga2O3 passivated samples were also discussed in this study. The gallium oxide films underwent an amorphous-to-crystalline phase transformations as the annealing temperature was increased above 550 °C. With an annealing temperature increased from 450 to 850 °C, the thickness of an interfacial silicon oxide layer increased from 2 to 7.4 nm; the interface state density, Dit, decreased from 4.21 × 1011 to 1.53 × 1011 eV−1 cm−2 and the effective oxide charge density, Qeff, changed from −3.7 × 1010 to 1.1 × 1011 cm−2 respectively. The Dit dominated the films passivation effect of the gallium oxide films with increasing annealing temperatures. The residual gallium hydroxide can act as a hydrogen reservoir for hydrogen diffusion and the interface hydrogenation play an important role in the Dit decrease.

High-Efficiency Silicon/Organic Heterojunction Solar Cells with Improved Junction Quality and Interface Passivation.

Silicon/organic heterojunction solar cells (HSCs) based on conjugated polymers, poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS), and n-type silicon (n-Si) have attracted wide attention due to their potential advantages of high efficiency and low cost. However, the state-of-the-art efficiencies are still far from satisfactory due to the inferior junction quality. Here, facile treatments were applied by pretreating the n-Si wafer in tetramethylammonium hydroxide (TMAH) solution and using a capping copper iodide (CuI) layer on the PEDOT:PSS layer to achieve a high-quality Schottky junction. Detailed photoelectric characteristics indicated that the surface recombination was greatly suppressed after TMAH pretreatment, which increased the thickness of the interfacial oxide layer. Furthermore, the CuI capping layer induced a strong inversion layer near the n-Si surface, resulting in an excellent field effect passivation. With the collaborative improvements in the interface chemical and electrical passivation, a competitive open-circuit voltage of 0.656 V and a high fill factor of 78.1% were achieved, leading to a stable efficiency of over 14.3% for the planar n-Si/PEDOT:PSS HSCs. Our findings suggest promising strategies to further exploit the full voltage as well as efficiency potentials for Si/organic solar cells.

Optically-free-standing InGaN microdisks with metallic reflectors

The optical properties of free-standing thin-film microdisks with NiAg metallic reflectors are compared with those with an indium tin oxide (ITO) interfacial layer. The microdisks have been fabricated by a combination of microsphere lithography and laser lift-off processes. Optical-pumped lasing from the microdisk with NiAg reflector has been observed, with reduced threshold and higher quality factor compared those with ITO layers, attributed to improved optical confinement due to the reflectivity of the Ag coating. The results are supported by three-dimensional (3D) finite-difference-time-domain (FDTD) simulations.

Two-terminal nonvolatile resistive switching memory devices based on n-CdSe NR/p-Si heterojunctions

Two-terminal nonvolatile resistive switching (RS) memory devices based on n-CdSe nanoribbon (NR)/p-Si heterojunction were fabricated. These memory devices exhibited excellent memory characteristics with high current ON/OFF ratio exceeding six orders of magnitude, long retention time over 104 s, and good endurance over 6 months. The capacitance-voltage (C-V) measurement was carried out to confirm the electrons traping and detrapping processes in interface oxide layer. The high-performance of memory devices and simple processing techniques will offer new opportunities for memory applications of one-dimensional nanomaterials.

Temperature Dependent Border Trap Response Produced by a Defective Interfacial Oxide Layer in Al2O3/InGaAs Gate Stacks.

Intentional oxidation of an As2-decapped (100) In0.57Ga0.43As substrate by additional H2O dosing during initial Al2O3 gate dielectric atomic layer deposition (ALD) increases the interface trap density (Dit), lowers the band edge photoluminescence (PL) intensity, and generates Ga-oxide detected by X-ray photoelectron spectroscopy (XPS). Aberration-corrected high resolution transmission electron microscopy (TEM) reveals formation of an amorphous interfacial layer which is distinct from the Al2O3 dielectric and which is not present without the additional H2O dosing. Observation of a temperature dependent border trap response, associated with the frequency dispersion of the accumulation capacitance and conductance of metal-oxide-semiconductor (MOS) structures, is found to be correlated with the presence of this defective interfacial layer. MOS capacitors prepared with additional H2O dosing show a notable decrease (∼20%) of accumulation dispersion over 5 kHz to 500 kHz when the measurement temperature decreases from room temperature to 77 K, while capacitors prepared with an abrupt Al2O3/InGaAs interface display little change (<2%) with temperature. Similar temperature-dependent border trap response is also observed when the (100) InGaAs surface is treated with a previously reported HCl(aq) wet cleaning procedure prior to Al2O3 ALD. These results point out the sensitivity of the temperature dependence of the border trap response in metal oxide/III-V MOS gate stacks to the presence of processing-induced interface oxide layers, which alter the dynamics of carrier trapping at defects that are not located at the semiconductor interface.

Defect distribution and Schottky barrier at metal/Ge interfaces: Role of metal-induced gap states

The defect distribution and Schottky barrier at metal/Ge interfaces were studied using first-principles calculation. It was shown that the defect density markedly increases around the interface owing to the stabilization caused by the hybridization of defect electronic states with metal-induced gap states (MIGS) and by the associated small elastic energy loss around the interface. By comparing the formation energies of various defects at a variety of metal/substrate interfaces, we showed that MIGS not only control the Schottky barrier but also promote a defect-density increase at most metal/semiconductor interfaces. Moreover, we showed that interface oxide layers block MIGS penetration into the Ge substrate and promote the observed breakdown of Fermi-level pinning.

The influence of magnesium oxide interfacial layer on photovoltaic properties of dye-sensitized solar cells

In the present study, to enhance the power conversion efficiency of the DSSCs, we introduce MgO insulating layers at the interface between TiO2 and electrolyte to decrease charge recombination rate by suppressing the electron transfer from TiO2 to the electrolyte. The thickness of the MgO layer plays a vital role in the kinetics of dye-sensitized solar cells and affects their overall efficiency. The cell with optimized thickness of MgO layer exhibits the highest conversion efficiency (η = 5.12 %) with a high short-circuit current density (18.15 mA/cm2) and open-circuit voltage (0.571 V). Open-circuit voltage decay measurement results verify the improvement of the electrons lifetime in the DSSCs fabricated with surface-modified photoanodes due to the retarding the charge recombination. In order to explore the reasons for the J SC improvement, incident photon-to-current conversion efficiency measurement was taken. Our results show that the enhancement in the photoinjected electron lifetime can contribute to an increase in the electron collection efficiency, leading to the improved J SC value. Furthermore, the enhancement in the photoinjected electron recombination rate is also demonstrated by electrochemical impedance spectroscopy.

The Effect of Substrate Surface Condition on Atomic Layer Deposited Alumina Passivation Films

Aluminum oxide (Al2O3) films have been wildly investigated due to the excellent surface passivation for the electrical device. Both hydrogen-terminated and pre-oxidized silicon surfaces were prepared before Al2O3 films deposition. Combining chemical environment analysis with the effective minority lifetime data, the effect of the surface conditions on the Al2O3 films passivation was discussed. The HF sample with hydrogen-terminated substrate surface had a higher minority carrier lifetime (about 721 μs) than the H2SO4+H2O2 sample with pre-oxidized substrate surface (about 631 μs). The H atoms played an important role in improving the passivation effect. And the importance of the interfacial oxide layer to Al2O3 films passivation was validated too.

Frequency and Voltage-Dependent Dielectric Properties and AC Electrical Conductivity of (Au/Ti)/Al2O3/n-GaAs with Thin Al2O3Interfacial Layer at Room Temperature

An (Au/Ti)/Al2O3/n-GaAs structure with thin (30 A) interfacial oxide layer (Al2O3), formed by atomic layer deposition technique is fabricated to investigate both frequency and applied bias voltage dependences of real and imaginary parts of dielectric constant (e′ and e′′) and electric modulus (M ′ and M ′′), loss tangent tan δ and ac electrical conductivity σAC in a wide frequency range from 1000 Hz to 1 MHz at room temperature. The dielectric properties of the (Au/Ti)/Al2O3/n-GaAs metal-insulator-semiconductor structure are obtained using the forward and reverse bias capacitance-voltage (C-V ) and conductance-voltage (G/ω-V ) measurements in the applied bias voltage range from –4 V to +4 V, at room temperature. Experimental results show that the dielectric parameters were strongly frequency and voltage dependent. For each frequency the (C-V ) plots show a peak and the change in frequency has effect on both the intensity and position of the peak. e′, e′′ and tan δ decrease with increasing frequency, whereas σAC increases with increasing frequency at applied bias voltage. M ′ increases with the increasing frequency and reaches a maximum. M ′′ shows a peak and peak position shifts to higher frequency with increasing applied voltage. It can be concluded that the e′, e′′, tan δ, M ′, M ′′ and σAC values of the (Au/Ti)/Al2O3/ n-GaAs structure are strongly dependent on both the frequency and applied bias voltage especially in the depletion and accumulation region. Also, the results can be deduced to imply that the interfacial polarization is easier at low frequencies, therefore contributing to the deviation of dielectric properties and AC electrical conductivity of (Au/Ti)/Al2O3/n-GaAs structure.

Effect of vanadium oxide interfacial layer for electrical contact on p-type silicon

Vanadium oxide interfacial layer between p-type silicon and indium tin oxide was studied as a hole transfer layer in solar cell application. The vanadium oxides deposited by sputtering technique with various conditions were investigated in terms of gap states using spectroscopic ellipsometry. As the Ar gas flow rate increases from 10 sccm to 40 sccm, the gap state of vanadium oxide thin films was reduced, and then it results in decrease of current due to reduction of carriers from p-type semiconductor to electrode for the solar cell applications. In the vanadium oxide films deposited by oxygen gases as reactive gas, a strong confinement of gap state near 1.7 eV as a transition energy appears, and this results in decreasing of total amount of density of states of interfacial layer. In the silicon solar cells with the vanadium oxide thin films deposited at 30 sccm Ar gas flow rate as an interfacial layer between indium tin oxide and p-type Si, it appears that the photoelectric conversion efficiency increases up to about 10% more than that of solar cell without interfacial layer.

High-Performance Perovskite Solar Cells Engineered by an Ammonia Modified Graphene Oxide Interfacial Layer.

PSS)-GO: NH3/CH3NH3PbI3-xClx/phenyl C61-butyric acid methyl ester (PCBM)/(solution Bphen) sBphen/Ag improves their performance and perovskite structure stability significantly. The fabricated devices with a champion PCE up to 16.11% are superior in all the performances in comparison with all the reference devices without the GO:NH3 layer. To understand the improved device performances, synchrotron-based grazing incidence X-ray diffraction (GIXRD), scanning electron microscopy (SEM), ultraviolet photoelectron spectroscopy (UPS), X-ray photoelectron spectroscopy (XPS), and UV-visible absorption measurements have been conducted on perovskite films on different substrates. It was found that these improvements should be partially attributed to the improved crystallization and preferred orientation order of peovskite structure, partially to the improved morphology with nearly complete coverage, partially to the enhanced optical absorption caused by the PSS-GO:NH3 layer, and partially to the better matched energy-level-alignment at the perovskite interface. Furthermore, the device was shown to be more stable in the ambient condition, which is clearly associated with the improved peovskite structure stability by the GO:NH3 layer observed by the GIXRD measurements. All these achievements will promote more applications of chemically modified graphene oxide interfacial layer in the PSCs as well as other organic multilayer devices.

(Invited) TmSiO as a CMOS-Compatible High-k Dielectric

Novel materials are being aggressively researched for integration in high-k/metal gate CMOS technology, as innovations in the gate stacks are necessary to sustain scaling toward the end of the roadmap. In this paper, we discuss thulium silicate as a candidate dielectric for integration as interfacial layer, focusing on compatibility with the requirements in terms of both process integration and effects on electrical device characteristics. In particular, we demonstrate that thulium silicate provides advantages over conventional chemical oxide interfacial layers in terms of scalability and channel mobility.

Effect of additional electron acceptor in hybrid P3HT:PCBM:ZnO spin‐coated films for photovoltaic application

Concerted efforts need to be undertaken to overcome limited efficiencies and instability issues in order to ensure a niche for organic photovoltaics (OPVs) in the PV market. Recent improvements on tandem structures aside, in order to achieve further improvements it is sensible to construct test‐case scenarios on bulk heterojunction cells. One aspect, involving the low mobility of charge carriers, caused by the short exciton diffusion length in the active layer, has been targeted. In this regard, attempts to incorporate inorganic semiconductors into organic blends in hybrid organic solar cells, in various configurations, have so far been promising. In this work, ZnO nanoparticles were mixed into the poly (3‐hexylthiophene) (P3HT):[6,6]‐phenyl‐C61‐butyric acid methyl ester (PCBM) blend, and used as additional acceptors of electrons in the active layer. Metal–oxide interface layers between the active layer and ITO and the top contact layer, respectively, were introduced in the solar cell to compensate for environmental degradation. Thermo‐gravimetric analyses of the active layers revealed improved thermal stability of P3HT upon incorporating ZnO in the polymer matrix. The photovoltaic properties demonstrated that the addition of ZnO nanoparticles in the P3HT:PCBM bulk‐heterojunction solar cell causes an increase in the power conversion efficiency, while excessive loading of ZnO decreases the efficiency.

Enhanced stability of complementary resistance switching in the TiN/HfOx/TiN resistive random access memory device via interface engineering

This study shows that a majority (70%) of TiN/HfOx/TiN devices exhibit failed complementary resistance switching (CRS) after forming. In conjunction with the consistent observation of a large non-polar reset loop in the first post-forming voltage-sweep measurement, it is proposed that breakdown of the TiN/HfOx interfacial oxide layers (crucial in enabling CRS) and the accompanied formation of Ti filaments (due to Ti migration from the TiN cathode into the breakdown path) resulted in CRS failure and the observed non-polar reset behavior. This hypothesis is supported by the significant reduction or complete elimination of the large non-polar reset and CRS failure in devices with a thin Al2O3 layer incorporated at the TiN-cathode/HfOx or both TiN/HfOx interfaces. The higher breakdown field of the thin Al2O3 enables it to sustain the forming voltage until the forming process is interrupted, thus enabling CRS via oxygen exchange with the adjacent vacancy-type filament formed in the HfOx.

Frequency dependent negative capacitance effect and dielectric properties of swift heavy ion irradiated Ni/oxide/n-GaAs Schottky diode

The Ni/n-GaAs Schottky barrier diode having thin interfacial oxide layer was subjected to 25MeV C4+ ion irradiation at selected fluences. The in-situ capacitance and dielectric properties were investigated in the 1KHz to 5MHz frequency range. The results show a decrease in capacitance with increase in ion fluence at low frequencies. Interestingly, a negative capacitance effect was also observed in this frequency range in all the samples. As a consequence, changes were observed in parameters like series resistance, conductance, dielectric loss, dielectric constant, loss tangent and ac electrical conductivity. At high frequencies, the capacitance reaches the geometric value ‘C0’. The results were interpreted in terms of the generation of irradiation induced traps, carrier capture and emission from deep and shallow states and its frequency dependent saturation effects.

Interfacial native oxide effects on the corrosion protection of copper coated with ALD alumina

The effect of the interfacial air-formed native copper oxide layer on the corrosion protection of copper with 20nm Atomic Layer Deposited (ALD) alumina was investigated in 0.5M NaCl using electrochemical and surface analysis techniques. The results show that dissolution of the interfacial native oxide by a pre-treatment of the copper substrate with phosphoric acid is beneficial to the sealing property of the coating and to the corrosion resistance of the substrate exposed through channel defects. Time of Flight Secondary Ion Mass Spectrometry (ToF-SIMS) elemental depth profiling evidenced the modifications of the interfacial copper oxide on a pre-treated substrate including cleaning from organic contaminants. The beneficial effects of the pre-treatment include improved ALD nucleation and growth due to interface cleaning and decreased cathodic electrochemical activity (assigned to oxygen reduction) at the end of the channel defects exposing the substrate to the environment. Electrochemical Impedance Spectroscopy (EIS) analysis revealed a remarkably lower porosity of the bulk of the ALD alumina layers as compared to the coating/substrate interface, suggesting interfacial trenching as a major failure mechanism for the corrosion protection. Interfacial trenching can be reduced with a freshly re-grown interfacial oxide on the pre-treated substrate surface. The necessity for better controlling the interface chemistry for improved corrosion protection by ALD alumina is demonstrated.