Interface Trap Charge Research Articles

Impact of interface trap charges on dopingless tunnel FET for enhancement of linearity characteristics

For the first time, we have explored the effect of positive and negative interface trap charges on the dopingless device using charge plasma concept and named the proposed device as heterogeneous gate dielectric charge plasma tunnel field-effect transistor (HD-CP-TFET). The heterogeneous gate dielectric is considered to improve the ON-state current and device performance. The main intention of this work is to improve the drain current, transconductance characteristics along with linearity figure-of-merits (FOMs). A comparative analysis is done with conventional CP-TFET in the presence of interface trap charges (ITCs). From comparative results, it is found that the proposed device shows a better performance in the presence of interface trap charges. All the simulations are performed on ATLAS TCAD device simulator. The results show that the proposed device has a better tunneling current, transconductance (\(g_{\text {m}}\)), cut-off frequency (\(f_{\text {T}}\)), second-order voltage intercept point (VIP2), third-order voltage intercept point (VIP3), third-order input intercept point (IIP3), and third-order intermodulation distortion (IMD3). Thus, the proposed device (HD-CP-TFET) shows the better performance in the presence of interface trap charges and indicates that this device is suitable for low-voltage analog/RF applications.

Light-Stimulated Synaptic Devices Utilizing Interfacial Effect of Organic Field-Effect Transistors.

Synaptic transistors stimulated by light waves or photons may offer advantages to the devices, such as wide bandwidth, ultrafast signal transmission, and robustness. However, previously reported light-stimulated synaptic devices generally require special photoelectric properties from the semiconductors and sophisticated device's architectures. In this work, a simple and effective strategy for fabricating light-stimulated synaptic transistors is provided by utilizing interface charge trapping effect of organic field-effect transistors (OFETs). Significantly, our devices exhibited highly synapselike behaviors, such as excitatory postsynaptic current (EPSC) and pair-pulse facilitation (PPF), and presented memory and learning ability. The EPSC decay, PPF curves, and forgetting behavior can be well expressed by mathematical equations for synaptic devices, indicating that interfacial charge trapping effect of OFETs can be utilized as a reliable strategy to realize organic light-stimulated synapses. Therefore, this work provides a simple and effective strategy for fabricating light-stimulated synaptic transistors with both memory and learning ability, which enlightens a new direction for developing neuromorphic devices.

Morphological Contributions to Interfacial Charge Trapping and Nongeminate Recombination in Polymer Solar Cells Revealed by UV Light Soaking.

Nongeminate charge recombination occurs over a broad range of time scales in polymer solar cells and represents a serious loss channel for the performance and lifetime of devices. Multiple factors influence this process, including changes in morphology and formation of permanent defects, but individual contributions are often difficult to resolve from conventional experiments. We use intensity modulated photocurrent/photovoltage spectroscopy (IMPS/IMVS) to investigate nongeminate charge recombination in blends of poly[2,6-(4,4-bis-(2-ethylhexyl)-4 H-cyclopenta [2,1- b;3,4- b']dithiophene)- alt-4,7(2,1,3-benzothiadiazole)] (PCPDTBT) and [6,6]-phenyl-C61-butyric acid methyl ester (PCBM) solar cells. PCPDTBT/PCBM devices are exposed to varying doses of UV light resonant with PCBM to induce small perturbations in the thin film morphology, namely local heating. IMPS/IMVS sweeps display signatures unique to degradation, that is, photocurrent and photovoltage leading the excitation light modulation appearing as positive phase shifts or 1st quadrant features in Bode and Nyquist representations, respectively. We assign this component to interface charging at purified PCPDTBT/PCBM phase boundaries that trap mobile charges and facilitate nongeminate recombination. Time- and frequency-domain drift-diffusion simulations are then used to model the perturbed photocurrent responses that show good agreement with experiments. Trap occupancies and their impact of photocurrent production are investigated using variable background (dc) excitation light intensities revealing increases of the 1st quadrant component in devices irradiated for longer times. No evidence of chemical degradation was observed from molecular spectroscopy and imaging experiments, and we conclude that morphological changes are chiefly responsible for larger nongeminate charge recombination yields as devices age. Lastly, we propose that the 1st quadrant IMPS/IMVS is a universal signature of morphology-related degradation, although its relative contribution may vary between material systems.

Mechanism of phosphorus passivation of near-interface oxide traps in 4H–SiC MOS devices investigated by CCDLTS and DFT calculation

Interfacial charge trapping in 4H–SiC MOS capacitors with P doped SiO2 or phospho-silicate glass (PSG) as a gate dielectric has been investigated with temperature dependent capacitance–voltage measurements and constant capacitance deep level transient spectroscopy (CCDLTS) measurements. The measurements indicate that P doping in the dielectric results in significant reduction of near-interface electron traps that have energy levels within 0.5 eV of the 4H–SiC conduction band edge. Extracted trap densities confirm that the phosphorus induced near-interface trap reduction is significantly more effective than interfacial nitridation, which is typically used for 4H–SiC MOSFET processing. The CCDLTS measurements reveal that the two broad near-interface trap peaks, named ‘O1’ and ‘O2’, with activation energies around 0.15 eV and 0.4 eV below the 4H–SiC conduction band that are typically observed in thermal oxides on 4H–SiC, are also present in PSG devices. Previous atomic scale ab initio calculations suggested these O1 and O2 traps to be carbon dimers substituted for oxygen dimers (CO=CO) and interstitial Si (Sii) in SiO2, respectively. Theoretical considerations in this work suggest that the presence of P in the near-interfacial region reduces the stability of the CO=CO defects and reduces the density of Sii defects through the network restructuring. Qualitative comparison of results in this work and reported work suggest that the O1 and O2 traps in SiO2/4H–SiC MOS system negatively impact channel mobility in 4H–SiC MOSFETs.

Detection of the Interface-Trap Charge Density and Lateral Nonuniformity of Through-Silicon Vias

Through-silicon via (TSV) technology has emerged as a key component of 3-D integrated circuits. As the integration density in a package increases, the nonlinear metal–oxide–semiconductor (MOS) capacitance in TSVs has a greater effect on the electrical performance of the devices. Imperfections due to the deposition of a dielectric layer are important factors which can change the characteristics of the MOS capacitance. This letter presents a method by which to detect the interface-trap charge density $\text{D}_{\mathbf {it}}$ and lateral nonuniformity (LNU) of imperfections in TSVs. The results of an analysis of a measured sample define $\text{D}_{\mathbf {it}}$ and LNU at the dielectric–semiconductor interface and demonstrate that the presence of LNU can be established by a negative $\text{D}_{\mathbf {it}}$ .

Impact of negative capacitance effect on Germanium Double Gate pFET for enhanced immunity to interface trap charges

In this work, a comprehensive drain current model has been developed for long channel Negative Capacitance Germanium Double Gate p-type Field Effect Transistor (NCGe-DG-pFET) by using 1-D Poisson's equation and Landau-Khalatnikov equation. The model takes into account interface trap charges and by using the derived model various parameters such as surface potential, gain, gate capacitance, subthreshold swing, drain current, transconductance, output conductance and Ion/Ioff ratio have been obtained and it is demonstrated that by incorporating ferroelectric material as gate insulator with Ge-channel, subthreshold swing values less than 60 mV/dec can be achieved along with improved gate controllability and current drivability. Further, to critically analyze the advantages offered by NCGe-DG-pFET, a detailed comparison has been done with Germanium Double Gate p-type Field Effect Transistor (Ge-DG-pFET) and it is shown that NCGe-DG-pFET exhibits high gain, enhanced transport efficiency in channel, very less or negligible degradation in device characteristics due to interface trap charges as compared to Ge-DG-pFET. The analytical results so obtained show good agreement with simulated results obtained from Silvaco ATLAS TCAD tool.

Stress induced degradation and reliability of Al2O3 thin film on silicon

The electrical properties of metal insulator semiconductor (MIS) devices with Al2O3 as dielectric layer deposited by reactive RF (radio frequency) magnetron sputtering were investigated using Capacitance-Voltage (C-V) and Current–Voltage (I-V) to determine the quality of oxide layer and oxide/silicon interface. To assess the reliability of Al2O3/Si interface constant current stress of 1 mA for varying time period was also investigated. The effect of post deposition annealing (PDA) on electrical behavior of Al/Al2O3/Si MOS (metal oxide semiconductor) capacitors was studied. Annealed devices show substantial improvement in interface trap charge density (Dit), fixed oxide charge density (Qf) and leakage current. Improved electrical and interface properties are achieved at annealing temperature of 425 °C. Incorporation of nitrogen gas improves the thermal stability of Al2O3 films which exhibited fewer shift in flat band voltage (Vfb) as compared to the samples grown in pure argon atmosphere. Breakdown voltage for nitrogen doped Al2O3 of 30 nm thin films was enhanced from 15 V to 19 V. Results indicate that reactive sputtering in N2 containing plasma is a promising approach as reduction in gate leakage current and power dissipation is utmost essential for integrating high-k material into semiconductor processing.

Reliability Issues of In2O5Sn Gate Electrode Recessed Channel MOSFET: Impact of Interface Trap Charges and Temperature

In this paper, reliability issues of In2O5Sn (indium–tin oxide: a transparent material) transparent gate recessed channel (TGRC)-MOSFET has been analyzed by considering the effect of interface trap charges (both positive and negative) present at the Si/SiO2 interface. Following device, characteristics are studied in terms of static, linearity, and intermodulation figure of merits. It is found that with the amalgamation of the transparent gate indium tin oxide on conventional recesses channel (CRC) MOSFET, it exhibits improved immunity against interface trap charges in comparison to CRC-MOSFET. In addition, the influence of ambient temperature (150–300 K) along with trap charges on TGRC-MOSFET has also been explored with an aim to analyze at which temperature of the device is more stable in the presence of interface defects (trap charges). Results obtained reveal that TGRC shows improved device performance at low temperature with trap charges being less influenced. Thus, this paper demonstrates that TGRC MOSFET can act as a promising candidate for low-power linear analog applications, where low temperature is required.

Assessment of read and write stability for 6T SRAM cell based on charge plasma DLTFET

To overcome the process variations due to random dopant fluctuations (RDFs) and complex annealing techniques a charge plasma based doping less TFET (CP-DLTFET) device has been proposed for designing of 6T SRAM cell. The proposed device also benefited by subthreshold slope, low leakage current, and low power supply. In this paper, to avoid the dependency of stability parameters of SRAM cell to supply voltage (Vdd), here N-curve metrics has been analyzed to determine read and write stability. Because N-curve provides stability analysis in terms of voltage and current as well as it gives combine stability analysis with the facility of an inline tester. Further, analyzing the N-curve metrics for different Vdd, cell ratio, and pull-up ratio assist in designing the configuration of transistors for the better read and write stability. Power metrics of N-curve gives the knowledge about read and write stability instead of using four metrics (SINM, SVNM, WTV, and WTI) of N-curve. Finally, in the 6T CP-DLTFET SRAM cell, read and write stability is tested by the interface trap charges (ITCs). The performance parameter of the 6T CP-DLTFET SRAM cell provides considerable read and write stability with less fabrication complexity.

Effect of nitrogen passivation/pre nitration on interface properties of atomic layer deposited HfO2

Properties and quality of thin films depend on the methods used to deposit it. ALD is a surface dependent process and is one of the best deposition techniques because of the control we have on the deposition. In ALD, quality of initial few layers depends on substrate surface. A well prepared substrate surface reduces problem of nucleation. In this work, we have reported nitrogen passivation/pre nitration of silicon wafer as a surface preparation technique for atomic layer deposition. The results obtained have shown that the nitrogen passivation/pre nitration have profound effect on electrical characteristics. Nitrogen passivation has been done at two different temperatures, 350 and 500 °C. Crystal structures and phase information of deposited HfO2 thin films were studied in passivated and non passivated cases using GI-X-ray diffraction, elemental composition was investigated by EDX. Capacitance–voltage (C–V), current–voltage (I–V) and conductance–voltage (G–V) measurements were performed. The density of the interface state charges (Dit) was computed from C–V and G–V characteristics. Leakage current has been reduced almost two fold by utilizing this technique indicating change in properties of deposited oxide and its interface with the substrate. Decrease in interface trap charges has also been observed. Density of interface traps has been decreased from 2.87 × 10−12 to 1.57 × 10−12 cm−2 eV−1. Crystallographic phase of the deposited films are also found different in two different temperatures, 350 and 500 °C of passivation. Crystallographic phase of the deposited films were determined from analysis of measured XRD spectra and are found different in two cases.

The effect of ionization and displacement damage on minority carrier lifetime

Based on 1 MeV electrons and 40 MeV Si ion irradiations, the contribution of ionization and displacement damage to the decrease in the minority carrier lifetime of gate controlled lateral PNP (GLPNP) transistors is investigated by gate sweeping (GS) technique. Molecular hydrogen is employed to increase the ionization radiation sensitivity and help to understand the relationship between the minority carrier lifetime and ionization damage. Experimental results show that 1 MeV electrons mainly induce ionization damage to GLPNP transistors, 40 MeV Si ions primarily produce displacement defects in silicon bulk. For 40 MeV Si ions, with increasing the irradiation dose, the densities of interface trap and oxide charge are almost no change, the minority carrier lifetime obviously decreases. The decrease of the minority carrier lifetime is due to bulk traps induce by 40 MeV Si ions. For 1 MeV electrons, with increasing the irradiation dose, the densities of interface trap and oxide charge for the GLPNP with and without soaked in H2 increase, and the minority carrier lifetime decreases. Compared with the GLPNP transistors without soaking in H2, the density of the interface traps the irradiated GLPNP transistors by 1 MeV electrons and soaked in H2 are larger and the minority carrier lifetime is lower. Therefore, both ionization and displacement damage can induce the decreases in the minority carrier lifetime including bulk minority carrier lifetime and surface minority carrier lifetime.

Radiation hardness of β-Ga2O3 metal-oxide-semiconductor field-effect transistors against gamma-ray irradiation

The effects of ionizing radiation on β-Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs) were investigated. A gamma-ray tolerance as high as 1.6 MGy(SiO2) was demonstrated for the bulk Ga2O3 channel by virtue of weak radiation effects on the MOSFETs' output current and threshold voltage. The MOSFETs remained functional with insignificant hysteresis in their transfer characteristics after exposure to the maximum cumulative dose. Despite the intrinsic radiation hardness of Ga2O3, radiation-induced gate leakage and drain current dispersion ascribed respectively to dielectric damage and interface charge trapping were found to limit the overall radiation hardness of these devices.

Time-dependent transport characteristics of graphene tuned by ferroelectric polarization and interface charge trapping.

Graphene-based field effect transistors (FETs) were fabricated by employing ferroelectric Pb(Mg1/3Nb2/3)O3-PbTiO3 (PMN-PT) as a gate insulator. The co-existing effects of ferroelectric gating and interface charge trapping on the transport properties of graphene were investigated with respect to the FET structure. The sheet resistance (Rs) of graphene shows a slight decay under a small applied voltage, which is much less than the coercive voltage of the ferroelectric PMN-PT, suggesting non-negligible charge trapping effects. Moreover, when the applied voltage is increased up to a value larger than the coercive voltage, Rs exhibits three states: an initial rapid change, followed by a slow nearly exponential evolution, and finally a saturated state either during the applied voltage is retained or after it is released. In particular, a high-resistance state is finally reached due to the ferroelectric gating, implying that ferroelectric effects dominate this process. The underlying physical mechanism was fully investigated to effectively address the observed evolution of time-dependent Rs. Such a finding provides us an opportunity to understand the co-existing effects of ferroelectric gating and charge trapping and tune the transport properties of graphene through the interface effects.

Temperature Associated Reliability Issues of Heterogeneous Gate Dielectric—Gate All Around—Tunnel FET

In this paper, the temperature associated reliability issues of heterogeneous gate dielectric-gate all around-tunnel FET (HD GAA TFET) has been addressed, and the results are simultaneously compared with gate all around tunnel FET (GAA TFET). This is done by investigating the effect of interface trap charges such as donor (positive interface charges) and acceptor (negative interface charges) at various operating temperatures on the device analog parameters and RF figure of merits. It is observed that, at high gate bias, TFET exhibits weak temperature dependence owing to the weak dependence of band to band tunneling phenomenon on the temperature in comparison to the large temperature variation for lower gate bias due to the temperature dependence of Shockley-Read-Hall (SRH) phenomenon. Results reveal that extremely high off current at elevated temperatures degarades the device performance, making the device less reliable for high-temperature applications. Moreover, at elevated temperature, the decrease in threshold voltage and intrnsic delay, and increase in cut off frequency is found, thereby upgrading the device characteristics. All the simulations have been done on ATLAS device simulator.

Interface charge trapping induced flatband voltage shift during plasma-enhanced atomic layer deposition in through silicon via

A Through Silicon Via (TSV) is a key component for 3D integrated circuit stacking technology, and the diameter of a TSV keeps scaling down to reduce the footprint in silicon. The TSV aspect ratio, defined as the TSV depth/diameter, tends to increase consequently. Starting from the aspect ratio of 10, to improve the TSV sidewall coverage and reduce the process thermal budget, the TSV dielectric liner deposition process has evolved from sub-atmospheric chemical vapour deposition to plasma-enhanced atomic layer deposition (PE-ALD). However, with this change, a strong negative shift in the flatband voltage is observed in the capacitance-voltage characteristic of the vertical metal-oxide-semiconductor (MOS) parasitic capacitor formed between the TSV copper metal and the p-Si substrate. And, no shift is present in planar MOS capacitors manufactured with the same PE-ALD oxide. By comparing the integration process of these two MOS capacitor structures, and by using Elastic Recoil Detection to study the elemental composition of our films, it is found that the origin of the negative flatband voltage shift is the positive charge trapping at the Si/SiO2 interface, due to the positive PE-ALD reactants confined to the narrow cavity of high aspect ratio TSVs. This interface charge trapping effect can be effectively mitigated by high temperature annealing. However, this is limited in the real process due to the high thermal budget. Further investigation on liner oxide process optimization is needed.

Effect of Interface Trap Charges on Performance Variation of Heterogeneous Gate Dielectric Junctionless-TFET

In this paper, we investigate the effect of interface trap charges on the variation of heterogeneous gate dielectric junctionless-tunnel FET (JL-TFET) by introducing both donor and acceptor type of localized charges at the semiconductor/insulator interface. In this regard, we have analyzed dc and analog/RF performance parameters for conventional and heterogeneous gate dielectric JL-TFET (HD JL-TFET) in terms of electric field, transfer characteristics, transconductance ( ${g}_{m}$ ), output transconductance ( ${g}_{\text {ds}}$ ), parasitic capacitances, device efficiency, cutoff frequency ( ${f}_{T}$ ), gain bandwidth product, and transconductance frequency product. Apart from these, linearity distortion parameters are also analyzed in the form of higher order transconductance coefficients ( ${g}_{m1}$ , ${g}_{m2}$ , ${g}_{m3}$ ), VIP2, VIP3, IMD3, and IIP3. For this, high-K gate dielectric material (HfO2) is used in the case of the HD JL-TFET to improve the performance of the device. All the simulations for both devices have been performed with the help of an ATLAS device simulator.

Impact of material properties and device architecture on the device performance for a gate all around nanowire tunneling FET

This paper systematically investigates the impact of gate dielectric, channel dimensional profile and the interface trap charge density on a homojunction indium–arsenide (InAs) gate all around nanowire tunneling FET (HJ-GAA-TFET). Device models were calibrated against the experimental data and simulations were performed to investigate the underlying physics. Device on-off (Ion/Ioff) ratio was considered as key figure-of-merit (FOM) to improve. It is observed that the off current (Ioff) is a weak function of dielectric constant, however, the on current (Ion) increases from 1.51 × 10−7 A µm−1 to 1.79 × 10−6 A µm−1 as the dielectric constant increases from SiO2 to La2O3. It was also observed that as the diameter increases, both Ion and Ioff increases. Ion/Ioff ratio is independent for higher channel lengths but as the channel length is reduced below 30 nm, Ioff increases causing degradation in Ion/Ioff ratio. Finally, the effect of interface traps was realised on the Ion/Ioff ratio. Interface traps impact the flat-band voltage causing a shift in the device performance. It is observed that as the trap density increases, Ioff degrades rapidly by ~3 orders in magnitude.

Proposal of alternative sensitive region for MOS based radiation sensors: Yb2O3

The purpose of this study is to investigate the usability of ytterbium oxide (Yb2O3) as a sensitive region/gate oxide in metal oxide semiconductor (MOS) based dosimeters and to determine the advantages and disadvantages of this device relative to its alternatives. For this purpose, amorphous Yb2O3 films were grown on p type Si by radio-frequency magnetron sputtering and aluminum (Al) was used as front and back ohmic contacts of the capacitor. Yb2O3 MOS devices were irradiated incrementally to the total dose of 70 Gy by 60Co radioactive source. The capacitance–voltage measurements were performed at low (100 kHz) and high (1 MHz) frequencies to examine the behavior of the traps. The sensitivity of the device for 70 Gy was obtained using flat band voltage shifts as 27.5 ± 1.1 and 28.1 ± 1.3 mV/Gy for 100 kHz and 1 MHz, respectively. The changes in the oxide trap charge densities in the studied dose between 0.5 and 70 Gy are in the ranges of (1.09 ± 0.04)× 1011–(1.23 ± 0.05) × 1012 cm−2 for 100 kHz and (−3.26 ± 0.08) × 1010–(8.16 ± 0.35) × 1011 cm−2 for 1 MHz. For both frequencies, there was no significant change in the interface trap charge densities over the applied dose and the density of these traps remained in order of 1011 cm−2 after each applied dose. The percentage fading were measured at only 1 MHz for evaluation of the device's dose storage capacity and the results varied from 4% (5 min) to −19% (50 min). An almost constant fading value was obtained after 20 min from irradiation. The capacitor's sensitivity was found to be higher than those of similar devices composed of HfO2, La2O3, SiO2, Sm2O3, and Y2O3. Yb2O3 would be a promising candidate for a new generation of MOS based radiation sensors.

Characterization of GigaRad Total Ionizing Dose and Annealing Effects on 28-nm Bulk MOSFETs

This paper investigates the radiation tolerance of 28-nm bulk ${n}$ and ${p}$ MOSFETs up to 1 Grad of total ionizing dose (TID). The radiation effects on this commercial 28-nm bulk CMOS process demonstrate a strong geometry dependence as a result of the complex interplay of oxide and interface charge trapping relevant to the gate-related dielectrics and the shallow trench isolation. The narrowest/longest channel devices have the most serious performance degradation. In addition, ${n}$ MOSFETs present a limited on-current variation and a significant off-current increase, while ${p}$ MOSFETs show a negligible off-current change and a substantial on-current degradation. The postirradiation annealing annihilates or neutralizes oxide trapped positive charges and tends to partly recover the degraded device performance. To quantify the effects of TID and postirradiation annealing, parameters including the threshold voltage, the free carrier mobility, the subthreshold swing, and the drain-induced barrier lowering are extracted.

Addressing the impact of rear surface passivation mechanisms on ultra-thin Cu(In,Ga)Se2 solar cell performances using SCAPS 1-D model

We present a (1-D) SCAPS device model to address the following: (i) the surface passivation mechanisms (i.e. field-effect and chemical), (ii) their impact on the CIGS solar cell performance for varying CIGS absorber thickness, (iii) the importance of fixed charge type (+/−) and densities of fixed and interface trap charges, and (iv) the reasons for discrete gains in the experimental cell efficiencies (previously reported) for varying CIGS absorber thickness. First, to obtain a reliable device model, the proposed set of parameters is validated for both field-effect (due to fixed charges) and chemical passivation (due to interface traps) using a simple M-I-S test structure and experimentally extracted values (previously reported) into the SCAPS simulator. Next, we provide figures of merits without any significant loss in the solar cell performances for minimum net −Qf and maximum acceptable limit for Dit, found to be ∼5×1012cm−2 and ∼1×1013cm−2eV−1 respectively. We next show that the influence of negative fixed charges in the rear passivation layer (i.e. field-effect passivation) is more predominant than that of the positive fixed charges (i.e. counter-field effect) especially while considering ultra-thin (<0.5μm) absorber layers. Furthermore, we show the importance of rear reflectance on the short-circuit photocurrent densities while scaling down the CIGS absorber layers below 0.5μm under interface chemical and field-effect passivation mechanisms. Finally, we provide the optimal rear passivation layer parameters for efficiencies greater than 20% with ultra-thin CIGS absorber thickness (<0.5μm). Based on these simulation results, we confirm that a negatively charged rear surface passivation with nano-point contact approach is efficient for the enhancement of cell performances, especially while scaling down the absorber thickness below 0.5μm.