Interface Trap Research Articles

Engineering oxygen vacancy-induced interface trap memristive effect in selenium-implanted gallium oxide

Engineering oxygen vacancy-induced interface trap memristive effect in selenium-implanted gallium oxide

Effect of NO annealing on radiation detection performance of Ni/SiO2/4H-SiC MOS capacitors

In this study, Ni/SiO2/4H-SiC metal-oxide-semiconductor (MOS) devices were fabricated, achieving high-energy resolution for alpha particle radiation detection. The SiO2/4H-SiC interface was treated with two different methods: i) annealing in N2 environment, ii) annealing in NO environment. Devices manufactured using the former method show lower dark currents than the latter. This difference is due to a decrease in trap density at the SiO2/4H-SiC interface caused by NO annealing, resulting in a higher barrier height for the device. The NO-30 exhibited a much higher energy resolution of 0.46%@5486 keV compared to 0.95%@5486 keV observed in N2-30, despite both devices exhibiting good energy linearity in response to alpha particles. The SiO2/4H-SiC interface trap density revealed a significant decrease after NO treatment, indicating NO treatment can effectively improve the electrical performance of 4H-SiC MOS devices. CCE analysis showed the NO-30 had a lower surface recombination field (13000 V/cm) compared to N2-30 (35000 V/cm), which improves the charge collection efficiency and energy resolution. This study provides a practical approach for enhancing the energy resolution of 4H-SiC MOS detectors.

Tailoring the Tunneling‐Effect‐Boosted Interfacial Charge Trapping via Effective Conjugation Length

AbstractHighly efficient charge injection and charge trapping stability of the tunneling layer are of desirable and practical importance to transistor memory applications. However, both of which can be contradictory to the nature properties of its material. It is herein demonstrated that lowering the energy mismatch of the tunneling layer by employing a longer conjugation length of the polymer can improve the charge injection efficiency, albeit the trapped charges will be easily diminished and finally losing its memory characteristics, and vice versa. To further elaborate and verify this concept, both materials are blended with distinct nature of properties as the tunneling layer in pentacene‐based transistor devices. As the results, the device using 300 nm SiO2 with optimum blending ratio displays a broad memory window of ≈77.6 V which is superior to the non‐blended tunneling layer carrying appropriate energy levels and band gap energy, not to mention, revealing fast operation time (≈1 s), low driving voltage (≈20 V), long retention (>104 s), and high switching stability over 50 cycles with on–off ratio of >104. Most importantly, this finding shed insight into the design of tunneling materials for advancing organic transistor memory technologies based on tunneling‐effect‐boosted interfacial charge trapping.

Enhancing Charge Trapping Performance of Hafnia Thin Films Using Sequential Plasma Atomic Layer Deposition.

We aimed to fabricate reliable memory devices using HfO2, which is gaining attention as a charge-trapping layer material for next-generation NAND flash memory. To this end, a new atomic layer deposition process using sequential remote plasma (RP) and direct plasma (DP) was designed to create charge-trapping memory devices. Subsequently, the operational characteristics of the devices were analyzed based on the thickness ratio of thin films deposited using the sequential RP and DP processes. As the thickness of the initially RP-deposited thin film increased, the memory window and retention also increased, while the interface defect density and leakage current decreased. When the thickness of the RP-deposited thin film was 7 nm, a maximum memory window of 10.1 V was achieved at an operating voltage of ±10 V, and the interface trap density (Dit) reached a minimum value of 1.0 × 1012 eV-1cm-2. Once the RP-deposited thin film reaches a certain thickness, the ion bombardment effect from DP on the substrate is expected to decrease, improving the Si/SiO2/HfO2 interface and thereby enhancing device endurance and reliability. This study confirmed that the proposed sequential RP and DP deposition processes could resolve issues related to unstable interface layers, improve device performance, and enhance process throughput.

Charge Carrier Dynamics at the Perovskite Interface with Self-Assembled Monolayers.

Self-assembled monolayers (SAMs) deposited on the hole-collecting electrodes of p-i-n perovskite solar cells effectively replace bulky hole transporting layers. However, the mechanism by which monolayers control the electronic processes and how they depend on the properties of the monolayer molecules remain poorly understood. In this study, we developed a simplified perovskite solar cell imitator with blocked electron extraction to investigate the photocurrent dynamics between the perovskite and the hole-collecting ITO electrode. We investigated the photoluminescence and photovoltage dynamics under short laser pulse excitation and addressed the influence of bulky and monomolecular hole transport layers. Our findings reveal that the photovoltage dynamics is significantly affected by the properties of the transport and perovskite layers, which in turn depend on the methods of sample preparation and exploration. Photocurrent dynamics is determined by several processes, including charge carrier displacement in the local electric field, hole transport to ITO, trapping of holes in interface trap states, and electron-hole recombination at the interface. We propose a model that takes into account molecular dipole moments and their ionization potentials to partially explain the different influences of different monolayers on the hole extraction and interfacial recombination rates. Additionally, the photovoltage dynamics also strongly depends on the illumination of the sample and shows memory effects that persist over minutes and hours and are attributed to the redistribution of ions.

Mechanisms and models of interface trap annealing in positively-biased MOS devices

Abstract We propose a hydrogen anion (H$^-$) passivation mechanism of the interface trap annealing (ITA) in positively-biased metal-oxide-semiconductor (MOS) devices. It is demonstrated that, the protons (H$^+$) released in SiO$_2$ due to H$_2$ cracking on oxide traps can migrate into Si at relatively high temperature, therefore passivating the interfacial $P_b$ centers by capturing two electrons provided by the positive bias. This new mechanism explains the elimination temperature of about 100$^\circ$C in experiments, which is much lower than temperature above 220$^\circ$C predicted by the traditional H$_2$ passivation mechanism. We also derive analytic models of the ITA, based on the coupling transformation dynamics of oxide and interface traps, as well as the concept of hierarchically constrained dynamics in glassy materials. These models can universally describe a generation-to-elimination transition of $P_b$, and predict the enhanced elimination of $E'_\gamma$ as the annealing temperature is elevated. Moreover, we demonstrate that, the defect annealing models can be applied to analysis the nonmonotonic temperature dependence of the annealing of threshold voltage shift in nMOS devices. Our findings provide a theoretical basis for achieving the low temperature elimination of interface traps, and for setting the high temperature stages of accelerated aging and damage evaluations of MOS devices.

Impact of voltage and frequency on electrical characteristics of MIS capacitors with triphenylamine layer

This study examines the effect of triphenylamine (TPA) interlayers on the electrical properties of Al/TPA/p-Si metal-interlayer/insulator material-semiconductor (MIS) capacitors. Using Gaussian software, TPA molecular structure was optimized, and HOMO-LUMO energy levels were simulated. Capacitance-conductance-voltage (C-G-V) measurements were performed at room temperature over −4 V to +4 V and 50 kHz–700 kHz. AFM and SEM analysis showed TPA films were smooth with a uniform thickness of about 178 nm. The C-V characteristics revealed a frequency-dependent decrease in capacitance, indicating a continuous distribution of interface states. Barrier height (ΦB) increased from 0.305 eV at 50 kHz to 0.655 eV at 700 kHz, while the active interface trap density (Dit) decreased from 6.73 × 1012 eV−1 cm−2 to 3.23 × 1011 eV−1 cm−2. Additionally, the accumulating region exhibited low series resistance values (between 6.88 and 8.44 Ω). These results suggest that TPA thin films are effective for MIS capacitors.

On-demand performance optimization of AlGaN/GaN high electron mobility transistors using stoichiometric variation of dielectric alloy AlxTayO

The current research investigates the potential advantages of optimally combining wide bandgap Al2O3 with high dielectric constant (high-κ) Ta2O5 for gate dielectric applications. Various compositions of 10 nm AlxTayO oxide films are grown on the Al0.3Ga0.7N/GaN heterostructure by co-sputtering Al and Ta metals, followed by thermal oxidation at 500 °C. The average root-mean-square roughness of the grown oxide films is ∼1.2–1.4 nm compared to 0.4 nm for as-deposited metal. X-ray photoelectron spectroscopy and transmission electron microscopyconfirm the formation and thickness of the grown oxide films. The bandgap (Eg) of the oxide films calculated from O1s electron energy loss spectra show a linear increase from 4.85 eV for pure Ta2O5 to 6.4 eV for pure Al2O3. The dielectric constant (εox) calculated from capacitance–voltage (CG−VG) measurements decreases linearly from 25.7 for Ta2O5 to 7.9 for Al2O3. The interface trap density (Dit) is estimated from the frequency dispersion of capacitance–voltage (CG−VG) characteristics. The DC and radio frequency (RF) characteristics of AlxTayO/Al0.3Ga0.7N/GaN high electron mobility transistor (HEMT) devices are measured and compared with the Schottky HEMT devices (without any gate oxide). Compared to Schottky HEMT devices, AlxTayO/Al0.3Ga0.7N/GaN HEMT devices show superior DC characteristics, which helps us achieve maximum RF output power. Furthermore, the OFF-state measurements show that the AlxTayO/Al0.3Ga0.7N/GaN HEMT devices can sustain higher source-to-drain voltages, from a minimum of 88 V on pure Ta2O5 metal-oxide-semiconductor (MOS)-HEMTs to a maximum of 138 V on pure Al2O3 MOS-HEMTs before the dielectric breakdown happens, compared to a 57 V breakdown voltage on Schottky HEMT devices. An oxide variation of AlxTayO, with Al composition ratio of 0.34, shows an exceptional ION/IOFF ratio of 4 × 1011, a gate leakage current of 8 × 10−12 A/mm, a near-ideal subthreshold slope of 63.8 mV/dec, and the unity current gain frequency (fT) of 25.6 GHz.

Nitride spacer aided 0.15 μm AlGaN/GaN HEMT fabrication with optimized gate patterning process

I-line stepper is widely used in large scale device manufacturing with limited achievable critical dimension by itself. With the aid of the spacer sidewall, the critical dimension can be further shrunk down. Spacer sidewall aided process necessitates an additional deposition-etching process, which inevitably results in process related damage under the gate. This paper proposes an optimized spacer sidewall aided gate patterning procedure for 0.15 μm GaN High Electron Mobility Transistors (HEMTs) fabrication. The process is proved to be effective in improving device performance compared to conventional sidewall process by keeping first Si-rich SiN passivation layer integrity at the gate edge. Interface trap density (Dit) and mobility were extracted for both conventional sidewall process and the optimized one with different passivation layers at the gate edge, demonstrating a lower Dit and higher mobility using the optimized process with enhanced device performances, such as higher current, breakdown voltage, and stress state characteristics, compared to the conventional process, which is promising for mass production of 0.15 μm GaN HEMTs.

Isolation and focal treatment of brain aneurysms using interfacial fluid trapping.

Current approaches for localized intravascular treatments rely on using solid implants, such as metallic coils for embolizing aneurysms, or on direct injection of a therapeutic agent that can disperse from the required site of action. Here, we present a fluid-based strategy for localizing intravascular therapeutics that leverages surface tension and immiscible fluid interactions, to allow confined and focal treatment at brain aneurysm sites. We first show, computationally and experimentally, that an immiscible phase can be robustly positioned at the neck of human aneurysm models to seal and isolate the aneurysm's cavity for further treatment, including in wide-neck aneurysms. We then demonstrate localized delivery and confined treatment, by selective staining of cell nuclei within the aneurysm cavity as well as by hydrogel-based embolization in patient-specific aneurysm models. Altogether, our interfacial flow-driven strategy offers a potential approach for intravascular localized treatment of cardiovascular and other diseases.

Low-frequency noise in the Double SOI (DSOI) MOSFETs with back-gate control

In this paper, the impact of the back-gate voltage (Vb ) on the low-frequency (1/f) noise is evaluated for the 180 nm double silicon-on-insulator (DSOI) NMOS, fabricated with various thicknesses of first buried oxide (BOX1) layer (145/50 nm). Both positive and negative Vb increased the measured normalized drain current power spectral density (PSD) for more than ten-fold in DSOI standard devices with 145 nm BOX1, while the normalized PSD decreases with Vb going up in devices with 50 nm BOX1. By comparing with CNF+CMF model, interface trap density and the Coulomb scattering coefficient are extracted with the back-gate voltage applied. The interface trap density increases in standard devices for both positive and negative Vb , but decreases with increasing back-gate biasing from -10 V to 10 V in devices with 50 nm BOX1. The interface trap density shows a similar back-gate coupling effect with threshold voltage under the influence of different thickness of BOX1. The CNF and CMF noise variation under back-gate voltage can be explained by the significant fluctuation in drain current.

Enhancement of dielectric constant in Sm:Zr co-doped HfO2 films synthesized by cost-effective method

Sm, Zr co-doped HfO2 films were deposited on a p-type silicon wafer using a cost-effective spin coating method. The influence of Sm, Zr co-doping concentration variation on structural, compositional, morphological, and electrical properties was examined. The dominance of the orthorhombic phase (o-phase) in comparison to the monoclinic phase was noted to rise with the simultaneous increment of Sm doping concentration and decrement of Zr concentration. A decrease in oxygen vacancies was noted for all the Sm, Zr co-doped HfO2 films from XPS results. Nonporous and uniform distribution of grains was observed from Field Emission Scanning Electron Microscope (FESEM) and Atomic Force Microscopy (AFM) studies. Electrical studies of MOS capacitors based on Sm, Zr co-doped HfO2 films revealed a low leakage current. C-V studies exhibited an increment of dielectric constant and a decrement of interface trap densities. Further, to obtain insights into the microscopic features of Sm, Zr co-doped films, impedance and modulus studies have been performed. The obtained results imply the potential of tuning Sm, Zr co-doping concentrations in HfO2 towards stabilization of the orthorhombic phase and to enhance the dielectric constant of the films.

Impact of Deposition Temperature on Structural and Electrical Properties of Sputtered AlN/ Si (111) for CMOS compatible MEMS

Aluminium nitride (AlN) thin films are grown by reactive sputtering on Silicon (Si) with (111) orientation at low temperature (< 450 °C) for piezoelectric-based micro-electromechanical systems (MEMS). The grown AlN thin films were polycrystalline wurtzite hexagonal structure with a high texture coefficient for the (002) plane of orientation. The leakage current density by the current-voltage (I-V) measurement was found to be as low as 1.6 ×10-6Acm−2 in the grown films. The trapped charges are crucial in controlling these electrical characteristics, and low interface trap density (6.72 ×1010cm−2 eV) was observed for the sputtered AlN grown at a substrate temperature of 300 °C. This study on the structural and electrical properties of AlN/Si (111) at low substrate temperature is compatible with the complementary metal oxide semiconductor (CMOS) process for constructing piezoelectric-based MEMS devices for various applications.

A novel approach to enhancing performance and endurance in GeS2 OTS devices using amorphous carbon doped W2N electrodes

Three–dimensional (3D) cross-point (X–point) memory has gathered interest for its fast data processing and high density, achieved by stacking memory with a selector device to prevent misinterpretation. Ovonic threshold switching (OTS) is a promising selector due to its reversible switching behavior. Although, OTS devices typically employ transition metal nitrides (TMN) such as TiNx, TaNx, and WNx for electrodes owing to their good stability, high melting points, and low resistivity, TMNs can diffuse and degrade device performance by recrystallizing with chalcogenide alloys. Amorphous carbon (a–C) can be a good alternative electrode material due to its low roughness, cost–effectiveness, high work function (WF), and excellent thermal stability. However, the high resistivity of a–C (~ 150 mΩ–cm) increases threshold voltage (Vth), causing high power consumption. Therefore, combining both a–C and TMN materials can effectively obtain their advantages. This study explores the effect of varying a–C content in W2N electrodes on GeS2–based OTS selectors. The (W2N)1-xCx (0 ≤ x ≤ 0.25) electrodes were deposited using DC magnetron co–sputtering. The phase of (W2N)1-xCx (0 ≤ x ≤ 0.25) films transformed from polycrystalline to amorphous with increasing x. Devices with (W2N)1-xCx/GeS2/W2N structure showed decreased Vth and off current, improving from 4.8 to 3.8V and 8.0 to 4.17nA, respectively. The subthreshold slope, distance between traps, and interface trap density (Nit) were extracted using the Pool–Frenkel model. The reduced Vth may be attributed to a higher WF and lower Nit with increasing x. The device’s lifetime improved up to 1.0 × 109 pulses for the highest a–C content in (W2N)1-xCx (0 ≤ x ≤ 0.25) electrodes.

Improving bias stability of IGZO field-effect transistors through CF4 plasma treatment of Al2O3 dielectrics

In this study, the effects of the CF4 plasma treatment on the amorphous indium gallium zinc oxide (IGZO) material were explored. The electrical characteristics of the IGZO-based field-effect transistor (FET) were also thoroughly examined to analyze the influence of the plasma treatment. Excellent adhesion of the sol-gel-based IGZO semiconducting film was achieved owing to the strong dipole moment of the AlOxFy layer created by the surface treatment. In particular, X-ray photoelectron spectroscopy depth profiles and transmission electron microscopy electron energy loss spectroscopy analyses provided clear evidence that fluorine atoms diffused into the Al2O3 surface via the CF4 plasma treatment. The formation of an AlOxFy layer at the IGZO/Al2O3 interface is expected to be advantageous for reducing the interface trap density, thereby enhancing the critical transistor parameters. Additionally, the plasma-treated IGZO transistor demonstrated strong electrical bias stability under continuous gate bias stress conditions. Therefore, surface modification via CF4 plasma treatment is proposed to boost the stability and performance of the device, offering a straightforward approach for integrated thin-film transistor circuitry in advanced display applications.

Characterization of Trap States in AlGaN/GaN MIS-High-Electron-Mobility Transistors under Semi-on-State Stress

Devices under semi-on-state stress often suffer from more severe current collapse than when they are in the off-state, which causes an increase in dynamic on-resistance. Therefore, characterization of the trap states is necessary. In this study, temperature-dependent transient recovery current analysis determined a trap energy level of 0.08 eV under semi-on-state stress, implying that interface traps are responsible for current collapse. Multi-frequency capacitance–voltage (C-V) testing was performed on the MIS diode, calculating that interface trap density is in the range of 1.37×1013 to 6.07×1012cm−2eV−1 from EC−ET=0.29 eV to 0.45 eV.

Enhanced device performance of GaN high electron mobility transistors with in situ crystalline SiN cap layer

In this paper, a ∼2 nm in situ SiN cap layer on AlGaN barrier layer is grown, which is revealed to be crystalline using high-resolution cross-sectional transmission electron microscopy. Benefitting from superior interface quality of epitaxial crystalline SiN/AlGaN interface, the gate diodes with in situ SiN cap layer feature lower interface trap state density than that with GaN cap layer. By comparing the GaN high electron mobility transistors (HEMTs) with the conventional GaN cap layer, the GaN HEMTs with in situ SiN cap layer exhibit improved device performance, showing higher electron mobility, higher drain current, larger on/off current ratio, and higher transconductance. For breakdown characteristics, the devices with in situ crystalline SiN cap layer show prominent advantages over the GaN cap layer with a 30% breakdown voltage increase to 810 V.

Low-voltage organic field-effect transistors by using solution-processable high-κ inorganic-polymer hybrid dielectrics

Organic field-effect transistors (OFETs) incorporating hybrid high-κ inorganic Al2O3 and polymer dielectrics, including polyvinyl alcohol (PVA), polystyrene (PS), or polymethyl methacrylate (PMMA), through solution-processing techniques were fabricated. The analyses revealed that the high surface energy and hydrophilicity property of Al2O3 and PVA, and the relatively hydrophobic property of PS surface, hindered the performance of corresponding OFETs. The Al2O3/PMMA-based OFET achieved the optimized performance, with a threshold voltage of −2.7 V, a hole carrier mobility of 0.056 cm2/Vs, and a current on/off ratio of 1.0 × 104 at a low operating voltage of −5 V. Through analyzing the characteristics of leakage current, capacitance, contact resistance, and trap density of OFETs, we found that the PMMA-engaged films possessed the optimized electrical properties. The introduction of PMMA eliminated the interfacial trapping, thereby lowering the threshold voltage and enhancing the performance of the device. The COMSOL Multiphysics simulation was conducted to confirm the physical mechanism. The strategy of utilizing Al2O3/PMMA hybrid dielectric could simultaneously ensure the low operating voltage and good performance of OFET, while guaranteeing the low leakage current by the thick PMMA.

Efficiency improvement of ultrathin CIGS solar cells

In this paper we present an optimization of rear-passivation parameters (cell pitch, opening width, and interface trap density) in u-CIGS solar cell using TCAD tools. The proposed investigation exhibits a significantly enhanced in understanding the beneficial effect of the rear passivation in ultrathin cell on conversion efficiency and reliability compared to existing solutions in the literature. Firstly, the device was calibrated according to the fabricated model taking in to account all material properties and defects at interfaces and within the bulk of the cells. Additional simulations demonstrate notable enhancements in cell performance due to changes in absorber thickness and doping concentration. However, traps were identified at rear u-CIGS/Al2O3 interface as a key factor degrading conversion efficiency by promoting carrier recombination. Mitigating this mechanism is essential for improving device performance. Incorporating a negative fixed charge density in the rear passivation layer offers a promising solution, providing effective field-effect passivation to minimize minority carrier recombination at the rear surface. The proposed u-CIGS solar cell device achieves an impressive efficiency of 15 % using a cell pitch of 1.5 µm and opening width of 300 nm with a fixed bandgap.

Synergy of Ag and Interfacial Oxygen Vacancies on TiO2 for Highly Efficient Photocatalytic Production of H2O2.

Photocatalytic H2O2 production stands as a promising sustainable technology for chemical synthesis. However, rapid charge recombination and limited oxygen adsorption by photocatalysts often limit its efficiency. Herein, we demonstrate that the synergy of Ag and interfacial oxygen vacancies on TiO2 could overcome these challenges. The optimized Ag/TiO2-50 photocatalyst achieved an impressive H2O2 production rate of 12.9 mmol h-1 g-1 and maintained a steady-state concentration of 12.8 mM, significantly outperforming most TiO2-based photocatalysts documented in the literature. Detailed mechanistic studies, aided by TAS, in situ X-ray photoelectron spectroscopy (XPS), and in situ electron paramagnetic resonance (EPR) techniques, indicate that the oxygen vacancies at the Ag-TiO2 interface act as an interfacial hole trap, inducing a directional hole transfer. This, coupled with Ag acting as an electron acceptor, synergistically boosts the electron-hole separation. Additionally, the increased amount of oxygen vacancies at the Ag-TiO2 interface of Ag/TiO2-50 leads to enhanced O2 adsorption, thus contributing to its superior catalytic performance. This study provides valuable insights into interfacial traps in the charge transfer process and highlights the potential of interface regulation for achieving efficient photocatalytic conversion.