Interface State Density Research Articles

Current-voltage (I-V) characteristics of Au/n-Ge heterostructure based on cobalt phthalocyanine (CoPc) interlayer

The influence of cobalt phthalocyanine (CoPc) interlayer on the I-V measurements of Au/n-Ge (pristine) contacts is investigated. I-V characteristics reveals the decrease in the reverse leakage current of CoPc interlayer contacts than compared to contacts without interlayer. The Schottky barrier parameters were described using forward I-V measurements by assuming standard thermionic emission mechanism. The barrier height (BH) of the contact with CoPc interlayer is significantly improved than compared to pristine contact. The observed BHs of pristine and CoPc interlayer contacts are found to be 0.63 eV and 0.67 eV respectively. Reduced interface state density and altered space charges on the n-Ge surface reduces tunneling resistance, may account for the larger BH observed in contacts with CoPc interlayer than pristine contacts. The series resistance evaluated for the contacts using Cheung’s method shows its consistency with Norde method. The observed series resistance value of the Au/CoPc/n-Ge contacts found to be significantly smaller in magnitude than Au/n-Ge contacts. The current conduction mechanism of pristine contact and contact with interlayer was evaluated using double logarithmic I-V plot in the forward bias region. Three regions of conduction mechanisms are observed for Au/CoPc/n-Ge contacts. It is evident that the CoPc interfacial layer considerably changes the conduction mechanism from ohmic conduction to trap charge limited current (TCLC) mechanism at moderately high voltages. The associated transition in the conduction mechanism might be due to the presence of shallow traps (low energy traps) with exponential distribution at the CoPc/n-Ge interface.

High-low Kelvin probe force spectroscopy for measuring the interface state density.

The recently proposed high-low Kelvin probe force microscopy (KPFM) enables evaluation of the effects of semiconductor interface states with high spatial resolution using high and low AC bias frequencies compared with the cutoff frequency of the carrier transfer between the interface and bulk states. Information on the energy spectrum of the interface state density is important for actual semiconductor device evaluation, and there is a need to develop a method for obtaining such physical quantities. Here, we propose high-low Kelvin probe force spectroscopy (high-low KPFS), an electrostatic force spectroscopy method using high- and low-frequency AC bias voltages to measure the interface state density inside semiconductors. We derive an analytical expression for the electrostatic forces between a tip and a semiconductor sample in the accumulation, depletion, and inversion regions, taking into account the charge transfer between the bulk and interface states in semiconductors. We show that the analysis of electrostatic forces in the depletion region at high- and low-frequency AC bias voltages provides information about the interface state density in the semiconductor bandgap. As a preliminary experiment, high-low KPFS measurements were performed on ion-implanted silicon surfaces to confirm the dependence of the electrostatic force on the frequency of the AC bias voltage and obtain the interface state density.

Effect of annealing on forming-free bipolar resistive switching of Gd2O3 thin films

Oxide-based resistive switching devices are a promising candidate for non-volatile memory applications. Here, we present a Gd2O3-based non-volatile memory device deposited using e-beam evaporation. In order to know the effect of annealing on the device performance, the as-grown sample was annealed at 500 °C. The capacitance (C) – voltage (V) and conductance (G) – voltage (V) measurements were investigated in the range of 200 kHz to 1 MHz. It was observed that the C-V and G-V changes with frequency due to the presence of interface states. The effect of series resistance (Rs) and interface state density (Dit) was also investigated for both devices. Furthermore, the resistive switching was recorded at± 5 V. Both devices exhibit bipolar resistive switching with charge conduction mechanism ascribed to ohmic, space charge limited conduction, and trap-filled space charge limited conduction. Consequently, the annealed device displayed an improved resistance ratio of 102 and a stable endurance of up to 1000 cycles with better data retention of over 103 s.

First principles calculation of strain effects on the density of interface states in 4H-SiC

Even though the interface of SiO2/SiC can be improved by performing nitridation processes, it is unclear how interfacial traps are decreased or why this reduces the flat-band voltage. To discover the physical origin of the correlation between the SiO2/SiC interface traps and the oxidation processes, the effects of biaxial strain on the bandgap (Eg) of SiO2/4H-SiC (0001) were studied by first-principles calculations of the Heyd–Scuseria–Ernzerhof (HSE06) mixing function, with results closely corresponding to the experimental Eg of 4H-SiC. The compressive and tensile strains led to a change not only in the Eg, described in previous work but also in the total energy E0 of SiO2/4H-SiC (0001), where the structure reaches equilibrium at 2 % compression. We discussed in more detail that the size of the Eg is mainly affected by the O 2p state in SiO2 and the C 2p and Si 3p state in SiC in our works. These results indicate that the strain method can be used to adjust the Eg of SiO2/4H-SiC, thereby changing its interface state.

Cation exchange strategy to construct nanopatterned Zn:NiOx electrode with highly conductive interface for efficient inverted perovskite solar cells

Inorganic hole-transporting materials (HTMs) with excellent hole extraction and transfer properties are highly desirable for inverted perovskite solar cells (PSCs). However, the widely employed oxide HTMs (e.g., NiOx nanocrystal) often suffer from the low p-type conductivity and severe trap-assisted recombination at HTMs/perovskite interface, which significantly limits the final performance of PSCs. Herein, the facile template-assisted cation exchange strategy is developed to fabricate nanopatterned Zn:NiOx as efficient HTMs for PSCs, for the first time. Promisingly, by virtue of the advantageous 1D nanoscale architecture and synergistic substitutional Zn doping, high conductivity, high hole mobility and low interfacial charge trap states density have been achieved by such nanopatterned Zn:NiOx HTMs. These features endow the highly conductive interface for PSCs to accelerate hole extraction and minimize recombination loss. As a consequence, PSCs with nanopatterned Zn:NiOx deliver a champion efficiency of ≈20 % with open-circuit voltage of as high as 1.14 V. This work demonstrates and paves a new insight and avenue for the rational design of efficient oxide HTMs.

Interface-state suppression of AlGaN/GaN Schottky barrier diodes with post-anode-annealing treatment

Owing to the high density and high mobility of two-dimensional electron gas (2DEG) induced by strong spontaneous polarization and piezoelectric polarization effect, AlGaN/GaN Schottky barrier diodes (SBDs) with high output current density and low on-resistance have proved to be a promising candidate. Anode of GaN SBD is the core structure, which affects the device performance such as turn-on voltage, reverse current, on-resistance, and breakdown voltage. Therefore, idealized Schottky junction with low interface state density is very important in achieving high-performance GaN SBD. In this work, AlGaN/GaN SBD with low work-function metal W as anode is fabricated, and the post-anode-annealing (PAA) treatment is found to be effective in promoting the bonding reaction between anode metal and GaN in the anode region. Comparing with GaN SBDs without PAA treatment, the interface state density decreases from 9.48×10<sup>15</sup> eV<sup>–1</sup>·cm<sup>–2</sup> to 1.77×10<sup>13</sup> eV<sup>–1</sup>·cm<sup>–2</sup> after PAA treatment. The reverse leakage current is reduced by two orders, which ascribes to the idealized anode interface with low interface state density. Meanwhile, the influence of interface state on carriers in the forward conduction process is also suppressed, and the differential on-resistance of the fabricated GaN SBDs decreases from 17.05 Ω·mm to 12.57 Ω·mm. It is obvious that the PAA process proves to be an effective method to suppress the interface states density at M/S interface, thus significantly improving the performance of GaN SBD, which is the key technology in fabricating the high-performance GaN device.

Effects of High‐Pressure H2 and D2 Post‐Metallization Annealing on the Electrical Properties of HfO2/Si0.7Ge0.3

High‐pressure annealing (HPA) in both hydrogen (H2) and deuterium (D2) environments is attempted on HfO2/Si0.7Ge0.3 capacitors as a post‐metallization annealing (PMA) approach. As compared with conventional forming gas annealing (FGA), a dramatic reduction in the interface state density (Dit) is achieved after both H2‐ and D2‐HPA processes at the equivalent temperature (300 °C) and time (30 min) by effectively passivating the Ge‐induced dangling bonds at the interface region. Meanwhile, the stress‐induced leakage current characteristics are only improved by the D2‐HPA process, indicating that D‐passivation is more resistant to external electrical stress than H‐passivation. As the PMA temperature increases to 500 °C, both HPA further decreases the Dit, but a significant increase is observed for FGA. In addition, the PMA temperature‐dependent degradation of leakage current is less in HPA than in FGA.

Electrical Performance Enhancement and Low-Frequency Noise Estimation of In2O3-Based Thin Film Transistor Based on Doping Engineering

In this work, solution-derived InErO thin films were deposited to act as the channel layers of thin film transistors (TFTs). The effect of Er doping content on the morphology, oxygen defects, optical properties of indium oxide (In2O3) films, and electrical performance of InErO/Al2O3 TFTs was systematically investigated. Based on experimental results, it can be inferred that InErO-TFTs with 5% Er doping content has demonstrated improved electrical performance, including field effect mobility ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu _{\text {FE}}$ </tex-math></inline-formula> ) of 17.55 cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{{2}}\,\,\cdot \,\,\text{V}^{-{1}}\,\,\cdot \,\,\text{s}^{-{1}}$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I} _{\text{ON}}/{I} _{\text{OFF}}$ </tex-math></inline-formula> of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.70\times 10^{{7}}$ </tex-math></inline-formula> , a subthreshold swing (SS) of 0.16 V/dec and threshold voltage shift of 0.10 and 0.09 V under positive bias stress (PBS) and negative bias stress (NBS) for 1800 s, respectively. The illumination NBS (NBIS) measurements have indicated the degraded device stability by reducing the light wavelength, which can be due to the ionization of oxygen vacancies. Low-frequency noise (LFN) characterizations on devices have shown that the interfacial density of states of In2O3-based TFTs decreases after Er doping. To demonstrate the potential applications of InErO-TFTs in logic circuits, a resistor-loaded unipolar inverter based on InErO/Al2O3 has been integrated, demonstrating good dynamic response behavior and high gain of 10. These results have indicated the great potential of solution-driven InErO-based TFTs for future applications in low-cost and high-performance electronics.

ZnO varistors with low leakage current and high stability arrester with Ga doping

The insulation level of power equipment in power system is based on the overvoltage protection level of metal oxide arrester represented by zinc oxide valve blade. Owing to its superior nonlinear voltage current characteristics and surge energy absorption capacity, ZnO varistor is widely used as the core component of power system arrester. The electrical characteristics of ZnO varistors are determined by their complex microstructures and grain boundary characteristics. Therefore, to further improve the insulation level of power grid equipment, doping is required to further improve the grain boundary characteristics of ZnO varistors. In order to obtain more stable ZnO varistors, the stability characteristics of Ga doped ZnO varistors are investigated. The microstructural and electrical characteristics of the obtained experimental samples are tested by scanning electron microscope, voltage current nonlinear characteristics, capacitance voltage characteristics, X-ray diffraction spectrum, energy spectrum scanning, dielectric loss, and AC acceleration aging. The experimental results show that with the further increase of gallium doping, gallium ions occupy the vacancies on the zinc oxide lattice, increasing the interface state density, and improving the Schottky barrier height. On the one hand, the leakage current density of ZnO varistor is reduced, on the other hand, the migration of free electrons in the depletion layer is suppressed, and the stability of ZnO varistor in the high charge rate environment is improved. Aluminum ions are dissolved into the ZnO lattice to generate a large number of free electrons, thereby reducing the resistivity of ZnO grains, which can effectively reduce the residual voltage ratio of ZnO varistor when large current passes through it. When the doping amount of Ga reaches 0.6%, the leakage current is 0.84 μA/cm&lt;sup&gt;2&lt;/sup&gt;, the residual voltage ratio is 1.97, the nonlinear coefficient is 66, and the Schottky barrier height is 1.81 eV. At 115 ℃, AC accelerated aging voltages of 87% &lt;i&gt;E&lt;/i&gt;&lt;sub&gt;1 mA&lt;/sub&gt;, 89% &lt;i&gt;E&lt;/i&gt;&lt;sub&gt;1 mA&lt;/sub&gt; and 91% &lt;i&gt;E&lt;/i&gt;&lt;sub&gt;1 mA&lt;/sub&gt; are applied to the test sample separately. The aging time is 1000 h, and the aging coefficients are 0.394, 0.437 and 0.550 separately. This research will help to further improve the protection level of zinc oxide surge arresters, achieving the deep limitation of grid overvoltage, and improving the security and stability of power systems.

Quantitative Measurement of Interface State Density in Donor-Acceptor Polymer Transistors

Donor-Acceptor (D-A) polymer field-effect transistors (pFETs) are at the cutting edge of organic electronics. However, some fundamental cognition of interface states remains unquantified, particularly at different dynamic scales. In this study, the interface states of D-A polymer transistors are quantified using the dynamic pumping method. The experimental results indicate that the interface state density of the transistor is insensitive to the measurement pulse condition and stays within the range of 1012 1013 cm-2. The experiments described in this paper provide a quantitative analysis of interface states. This analysis can serve as effective guidance for optimizing future devices.

Germanium gate hydrogen-terminated diamond field effect transistor with Al2O3 dielectric layer

Investigation of germanium gate hydrogen-terminated (H-terminated) diamond field effect transistor (FET) with Al2O3 dielectric layer has been successfully performed. The device demonstrates a normally-on characteristics, whose maximum drain-source current density, threshold voltage, maximum transconductance, on/off ratio, subthreshold swing, capacitance, carrier density, saturation carrier mobility, fixed charge density and interface state density are of −37.3 mA/mm, 0.22 V, 6.42 mS/mm, 108, 134 mV/dec, 0.33 μF/cm2, 9.83 × 1012 cm−2, 97.9 cm2/V·s, 7.63 × 1012 cm−2 and 2.56 × 1012 cm−2·eV−1, respectively. This work is significant to the development of H-terminated diamond FET.

Investigation of the Electrical Properties of PAN-GO/p-Si Schottky Diode

In this article, the electrical properties of PAN-GO/p-Si Schottky diode were investigated in the dark at room temperature. Field-emission scanning electron microscopy (FE-SEM) was utilized to study the structure of the PAN:GO interfacial layer. Diode parameters were calculated according to thermionic emission theory. By using the I-V characteristic of the prepared PAN-GO diode, the ideality factor (n), barrier height (ФB) and series resistance (Rs) values were evaluated with the I-V method and Norde functions. The barrier height values calculated with the I-V and Norde function were found to be 0.767 eV and 0.761 eV, respectively. The ideality factor was found to be 2.078 from the I-V method. The series resistance value of the diode was calculated as 42 kΩ using Norde functions. Energy-dependence profile of interface state density was determined from the current-voltage characteristics by considering the voltage-dependence of barrier height and ideality factor The interface state density (Nss) values of the PAN-GO/p-Si Schottky diode are 9.5x1011 eV-1cm-2 for 0.35-Ev eV and 1.03x1011 eV-1cm-2 for 0.74-Ev eV. Experimental results approved that the PAN-GO interfacial layer improved the performance of metal-semiconductor Schottky diode in respect of low ideality factor, interface state density, and high barrier height and rectification rate.

Observation of Space Charge Limited Current in Schottky Diodes with V2O5 Interfacial Layer Prepared by Radio Frequency Magnetron Sputtering

Electrical properties of V2O5/n-Si Schottky barrier diodes prepared by rf magnetron sputtering of vanadium pentoxide (V2O5) on n-Si wafer have been investigated. The current-voltage (I–V) and capacitance-voltage (C-V) measurements of the diode have been performed in the dark at the room temperature. The saturation current (I0), ideality factor (n), barrier height (ΦB) values of the diode have been determined as 6.68x10-8 A, 1.35, and 0.755 eV, respectively. The series resistance (RS) values from Norde, Cheung and Nicollian & Brews methods have been determined as 199 Ω, 251 Ω, and 144 Ω, respectively. The energy distribution of interface state density (NSS) was determined, and the values of against the energy values of NSS in the vary between EC-0.462 eV and EC-0.713 eV were obtained 4.343x1016 eV-1 cm-2 and 3.282x1015 eV-1 cm-2, respectively. The barrier height and metal oxide thickness (ẟ) values using capacitance-voltage (C-V) measurements in the frequency of 1 MHz has also been calculated as 0.949 eV and 37.4 nm, respectively. The prepared diode showed abnormal diode characteristics, indicating the existence of a space-charge limited (SCL) current. From forward bias I-V characteristics, the ohmic, trapped filled space charge limited current (TFSCLC) and SCLC conduction behaviors were observed at low, middle, and high voltages, respectively. Experimental results indicated that the prepared V2O5 film on n-Si can be utilized in electronic applications.

Dark conduction mechanisms of PTQBDT based heterojunction diode

Al:LiF/PTQBT:PCBM/PEDOT:PSS/ITO/glass organic-based diode is fabricated with different weight ratios in PTQBT:PCBM active layer. The diodes D1, D2 and D3 are prepared using the precursor solution for spin coating process as 1:2, 1:3 and 1:4, respectively. Under dark, main diode parameters are extracted by conventional thermionic emission theory using the results of measurements. Parasitic resistance contribution, non-ideal barrier height formation and high values of ideality factor indicate possible effects of space charge limited current flow mechanism on forward biased characteristics. At saturated voltage region, series resistances are calculated and the results are evaluated according to Cheung’s method. The possible voltage sharing between interface layer and depletion region are also investigated by analysis of density of interface states. In addition, field effect is found in a major role on the reverse current flow and the mechanism is evaluated according to Schottky-Richardson model.

Improved performance of enhancement-mode GaN MIS-FET based on a self-terminating gate recess etching technique with in situ NH3 pre-treatment

Based on a self-terminating gate recess etching technique, we successfully fabricated a high-breakdown-voltage and high-threshold-voltage normally-off SiN/AlN/GaN-on-Si metal-insulator-semiconductor-field-effect-transistor (MIS-FET) with optimized PEALD-AlN (plasma-enhance-atomic-layer-deposition) protection layer and in situ NH3 pre-treatment. Compared with thermal-ALD-AlN, the PEALD-AlN protection layer could form a lower interface state density with the GaN channel. Moreover, the in situ NH3 pre-treatment performed in the PEALD system prior to PEALD-AlN deposition could further improve the interface quality. Using in situ NH3 pre-treatment and a PEALD-AlN protection layer, the fabricated SiN/AlN/GaN-on-Si MIS-FET exhibits a high-threshold-voltage of 2.60 V at I D of 1 μA mm−1 (6.57 V by linear extrapolation) and a high-breakdown-voltage of 1775 V.

The Electrical Characteristics and the Interface State Densities of Al/p-Si Structures with and Without the GO Insulator Layer

Introduction: The current-voltage (I-V) characteristics of the Al/p-type Si metal-semiconductor (MS) and Al/GO/p-type Si metal-oxide-semiconductor (MOS) structure was investigated at room temperature (300 K). Methods: The main electrical characteristics such as ideality factor (n), zero-bias barrier height (bo) and series resistance (RS) of Al/p-Si and Al/GO/p-type Si semiconductor structure obtained from different methods using I−V measurements Results: Experimental results show that the electrical properties obtained from Al/GO/p-type Si structure are I-V measurements generally slightly greater than those obtained from Al/p-type Si structure. Conclusion: However, the interface state densities resistance values obtained from Al/GO/p-Si structure are generally slightly smaller than those obtained from Al/p-type Si structure. The interface states (NSS) as energy distribution functions (ESS-EV) was obtained by using I-V measurements for both Al/p-type Si and Al/GO/p-type Si structure.

Interface state density distribution near conduction band edge at Al2O3/Mg-ion-implanted GaN interface formed after activation annealing using AlN cap layer

An interface state density (Dit) distribution near the conduction band edge (EC) at the Al2O3/Mg-ion-implanted GaN interface was measured after ion implantation, annealing with an AlN protective cap, and cap layer removal. Mg ions were implanted into n-GaN with a Si concentration of 6 × 1017 cm−3 at a maximum Mg concentration of 2 × 1017 cm−3, resulting in the maintenance of the n-type conduction in GaN even after the activation of Mg dopants. Activation annealing was carried out at 1250 °C for 1 min using an AlN cap layer. The complete removal of the AlN cap layer was accomplished by wet etching, which was confirmed by x-ray photoelectron spectroscopy. The photoluminescence spectrum showed donor–acceptor-pair emission after annealing, indicating the activation of Mg acceptors. By applying the capacitance–voltage method to a completed metal–oxide–semiconductor diode, we derived a continuous distribution of relatively low Dit below 5 × 1012 cm−2 eV−1, which increased monotonically toward EC in the range from EC − 0.15 to EC − 0.45 eV. Compared with the Dit distribution of the as-implanted sample, the density of the discrete level at EC − 0.25 eV generated by divacancies markedly decreased upon 1250 °C annealing.

ALD growth of ZnO on GaN: Schottky barrier height engineering using ZnO interlayer

Electrical properties of Pt/GaN Schottky diodes have been explored using ZnO interlayers (ILs) grown by thermal atomic layer deposition, which were systematically tuned by varying the growth temperature and thickness of ZnO ILs. For the 20-nm-thick ZnO ILs grown at different temperatures, the growth temperature of 100 °C showed the best rectifying characteristics. The thermionic field emission (TFE) model could explain the forward current characteristics for the growth temperatures of 80, 100 and 150 °C while the tunneling current became dominant for the growth temperature of 200 °C. For the ZnO ILs grown at 100 °C with different thicknesses, the barrier height decreased first and then increased with increasing the ZnO thickness. The samples revealing high interface state density showed the strong tunneling current. It is inferred from the result that both growth temperature and thickness of ZnO IL can be modulated to achieve good Schottky or ohmic contacts for GaN based devices.

Mobility degradation under a high effective normal field in an inversion layer of 4H-SiC (0001) metal–oxide–semiconductor structures annealed in POCl3

Mobility degradation under a high effective normal field (1 MV cm−1 < E eff < 2 MV cm−1) in an inversion layer of 4H-silicon carbide (SiC) (0001) metal–oxide–semiconductor field-effect transistors (MOSFETs) annealed in POCl3 is investigated by applying a negative body bias (0 V ≥ V BS ≥ −40 V). The effective channel mobility (μ eff) is proportional to E eff −2.3–−2.2 in the range 1 MV cm−1 ≤ E eff. On the basis of the obtained results, the authors propose that the mobility degradation in the high-E eff region is caused by strong surface roughness scattering in SiC MOSFETs with a very low interface state density.

Interface engineering of p-type quaternary metal oxide semiconductor interlayer-embedded β-Ga2O3 Schottky barrier diode

Here, we propose a p-type copper aluminum oxide (p-CuAlO2) interlayer for the high breakdown and low leakage current of β-Ga2O3 Schottky barrier diodes (SBDs). The XPS and TEM analysis was employed to confirm the surface elemental compositions, chemical states, and microstructural properties of RF sputtered p-CuAlO2 thin films on β-Ga2O3. The electrical and carrier transport properties of Pt/β-Ga2O3 SBD and Pt/p-CuAlO2/β-Ga2O3 heterojunction (HJ) were studied by using current-voltage (I–V) and capacitance-voltage (C–V) measurements. In comparison to the SBD, the HJ displayed superior rectifying behavior, lower reverse leakage current, lower on-resistance, and a larger turn-on voltage. Higher barrier height (BH) was attained for the HJ compared to the SBD, which enabled the p-CuAlO2 interlayer to alter the barrier height. The reverse breakdown voltage of HJ increased by nearly 300 V compared to SBD and reached a maximum of 922 V. The BH values were extracted from the I–V, Hernandez, Cheung's, Mikhelashvili, Norde's, Chot, and surface potential methods found the values are comparable with one another, which indicates their steadiness and validity. The energy distribution profile of the interface state density (NSS) of the HJ decreases compared to the SBD, which indicates that the p-CuAlO2 interlayer facilitated the reduction of NSS of the Pt/β-Ga2O3 SBD interface. The forward log(I)-log(V) plot of the SBD and HJ reveals the ohmic nature at low voltage regions and space-charge limited conduction at higher voltage regions. Results reveal that the reverse leakage current conduction mechanism of the SBD and HJ showed that the Poole-Frenkel conduction mechanism is found to be governed in the lower voltage region, whereas the Schottky conduction mechanism is found to be directed in the higher voltage region, respectively. These outcomes point out that the p-CuAlO2 is a high potential candidate material for forming a heterojunction with β-Ga2O3.