Intellectual Property Cores Research Articles

SoC-based real-time SVM classification with integrated training using HLS and PYNQ

Support Vector Machines (SVM) are widely used techniques in the field of classification problems because of their ability to effectively deal with datasets that have complex non-linear structures and a high dimensionality. The compute-intensive training algorithm associated with SVM makes it challenging to keep an up-to-date model that accurately reflects the characteristics of newly arriving data points in real-time systems. This paper proposes a novel training algorithm for incremental learning from large datasets, based on a variant of Sequential Minimal Optimization (SMO). High-Level Synthesis (HLS) was used for implementing the Field Programmable Gate Array (FPGA) based Intellectual Property (IP) Core, which includes the computationally intensive kernel computation portion of the training algorithm. In addition to the kernel computation, the inference phase of the SVM classifier is built into the IP core, and its use can be switched on the fly. The computational latency and memory bandwidth of an IP core are optimized using loop pipelining and DMA burst data transfer. With the help of hardware/software co-design, the IP core is integrated into the design of a flexible and re-usable System on Chip (SoC) called PYNQ Overlay. The experiments show that the overlay outperforms the embedded processor, multiple hardware SVM classifiers, and hardware accelerated Convolutional Neural Networks (CNN) in terms of real-time efficiency. The Overlay makes much less use of the resources available on the chip in comparison to the majority of the CNN accelerators. The overlay achieves an average classification accuracy that is only 1% lower than that of an ARM Cortex-A9 processor, according to experimental results on six datasets. Furthermore, it can increase training speed by an average of 31.82x and inference speed by an average of 31.74x. In addition, the proposed Overlay design achieves a 2.3x improvement in average training speed, as measured in Mega bits per second, compared to existing SVM training implementations, along with incremental learning and multi-class classification support.

FPGA-Flux Proprietary System for Online Detection of Outer Race Faults in Bearings

Online fault detection in industrial machinery, such as induction motors or their components (e.g., bearings), continues to be a priority. Most commercial equipment provides general measurements and not a diagnosis. On the other hand, commonly, research works that focus on fault detection are tested offline or over processors that do not comply with an online diagnosis. In this sense, the present work proposes a system based on a proprietary field programmable gate array (FPGA) platform with several developed intellectual property cores (IPcores) and tools. The FPGA platform together with a stray magnetic flux sensor are used for the online detection of faults in the outer race of bearings in induction motors. The integrated parts comprising the monitoring system are the stray magnetic flux triaxial sensor, several developed IPcores, an embedded processor for data processing, and a user interface where the diagnosis is visualized. The system performs the fault diagnosis through a statistical analysis as follows: First, a triaxial sensor measures the stray magnetic flux in the motor’s surroundings (this flux will vary as symptoms of the fault). Second, an embedded processor in an FPGA-based proprietary board drives the developed IPcores in calculating the statistical features. Third, a set of ranges is defined for the statistical features values, and it is used to indicate the condition of the bearing in the motor. Therefore, if the value of a statistical feature belongs to a specific range, the system will return a diagnosis of whether a fault is present and, if so, the severity of the damage in the outer race. The results demonstrate that the values of the root mean square (RMS) and kurtosis, extracted from the stray magnetic field from the motor, provide a reliable diagnostic of the analyzed bearing. The results are provided online and displayed for the user through interfaces developed on the FPGA platform, such as in a liquid crystal display or through serial communication by a Bluetooth module. The platform is based on an FPGA XC6SLX45 Spartan 6 of Xilinx, and the architecture of the modules used are described through hardware description language. This system aims to be an online tool that can help users of induction motors in maintenance tasks and for the early detection of faults related to bearings.

A novel Ethernet based processing system for remote source harmonic detection

This work is carried out to objectively establish a new method to detect harmonics and measure the total harmonic distortion (THD) in a remote source, such as a high voltage transformer. The proposed approach utilized embedded design techniques to construct an embedded processor system with Ethernet intellectual property core to acquire data from a remote harmonics source. The designed system has several notable merits, namely, it is portable that can be applied in the work field, and it avoids workers from being subject to a hazard high voltage shock as well as its simplicity and high accuracy. The harmonics detection and analysis are achieved by inserting a microcontroller system near the high voltage transformer to acquire the necessary data and transmit it to a remote embedded processor system that is used to detect and analyze the harmonics. The microcontroller and the processor systems are connected by a wide-area network (WAN) through Ethernet and transmission control protocol/internet protocol (TCP/IP) protocols. The processor system is accommodated to perform 128 points fast Fourier transform for harmonics detection. Matlab simulations are used to validate the results. It is found that the results match very accurately the simulation results with an error of less than 0.02%.

PSO based exploration of multi-phase encryption based secured image processing filter hardware IP core datapath during high level synthesis

Image processing filter intellectual property (IP) cores perform different critical operations on images such as blurring, sharpening, edge detection, etc., which are essential functions in several multimedia systems. The design process of the image filter cores as a dedicated IP needs to consider multiple objectives such as area, delay, and security against various hardware threats such as IP piracy (counterfeiting and cloning) and fraudulent claim of IP ownership during design space exploration (DSE) in high level synthesis (HLS). This paper presents the following novelties: (a) particle swarm optimization (PSO) driven exploration of secured image processing filter IP core datapath architecture during HLS capable of providing detective control against IP piracy threat (b) the proposed approach incorporates embedding of covert security constraints based on the proposed multi-phase encryption algorithm during performing area-delay tradeoff via PSO based DSE. The proposed approach achieves stronger security in terms of digital proof of > 2X and higher tamper tolerance as well as attains a lower design cost of 56.92% in terms of area-delay than recent approaches. The proposed approach also achieves optimal solution as evident from the optimality analysis performed on metrics such as generational distance, spacing, spreading, and weighted sum.

DycSe: A Low-Power, Dynamic Reconfiguration Column Streaming-Based Convolution Engine for Resource-Aware Edge AI Accelerators

Edge AI accelerators are utilized to accelerate the computation in edge AI devices such as image recognition sensors on robotics, door lockers, drones, and remote sensing satellites. Instead of using a general-purpose processor (GPP) or graphic processing unit (GPU), an edge AI accelerator brings a customized design to meet the requirements of the edge environment. The requirements include real-time processing, low-power consumption, and resource-awareness, including resources on field programmable gate array (FPGA) or limited application-specific integrated circuit (ASIC) area. The system’s reliability (e.g., permanent fault tolerance) is essential if the devices target radiation fields such as space and nuclear power stations. This paper proposes a dynamic reconfigurable column streaming-based convolution engine (DycSe) with programmable adder modules for low-power and resource-aware edge AI accelerators to meet the requirements. The proposed DycSe design does not target the FPGA platform only. Instead, it is an intellectual property (IP) core design. The FPGA platform used in this paper is for prototyping the design evaluation. This paper uses the Vivado synthesis tool to evaluate the power consumption and resource usage of DycSe. Since the synthesis tool is limited to giving the final complete system result in the designing stage, we compare DycSe to a commercial edge AI accelerator for cross-reference with other state-of-the-art works. The commercial architecture shares the competitive performance within the low-power ultra-small (LPUS) edge AI scopes. The result shows that DycSe contains 3.56% less power consumption and slight resources (1%) overhead with reconfigurable flexibility.

ANN-Aided Data-Driven IGBT Switching Transient Modeling Approach for FPGA-Based Real-Time Simulation of Power Converters

This article develops a novel feedforward neural networks (FFNNs)-based device-level model from a physical insulated-gate bipolar transistor (IGBT) model dataset by the proposed artificial neural network (ANN)-aided data-driven IGBT switching transient modeling approach, so that the physics-based IGBT models can be indirectly integrated into field programmable gate array (FPGA)-based real-time simulation of power converters. The main concept is to fit the turn-on/turn-off transient waveforms generated from a physics-based IGBT model by using multiple FFNNs with the same structure but different coefficients. Each FFNN is trained by a dataset covering the transient voltage/current values corresponding to all possible operating conditions at a given discrete time point during a transient. All FFNN coefficients are stored on FPGA. By applying the corresponding FFNN coefficients at each simulation time step, the switching transient waveforms can then be accurately reproduced. The proposed FFNN-based device-level model is designed into two intellectual property (IP) cores at 200 MHz with a fully pipelined structure, which allows the model to authentically reproduce transient waveforms with a 5-ns resolution. A four-phase floating interleaved boost converter (FIBC) is selected as a case study and simulated on a NI-PXIe FlexRIO FPGA real-time platform. The FPGA-based experimental results are compared with that from the LTspice offline simulator, which enables the validation of the accuracy and effectiveness of the proposed modeling approach for real-time simulation of power converters.

Research and Implementation of High Computational Power for Training and Inference of Convolutional Neural Networks

Algorithms and computing power have consistently been the two driving forces behind the development of artificial intelligence. The computational power of a platform has a significant impact on the implementation cost, performance, power consumption, and flexibility of an algorithm. Currently, AI algorithmic models are mainly trained using high-performance GPU platforms, and their inferencing can be implemented using GPU, CPU, and FPGA. On the one hand, due to its high-power consumption and extreme cost, GPU is not suitable for power and cost-sensitive application scenarios. On the other hand, because the training and inference of the neural network use different computing power platforms, the data of the neural network model needs to be transmitted on platforms with varying computing power, which affects the data processing capability of the network and affects the real-time performance and flexibility of the neural network. This paper focuses on the high computing power implementation method of the integration of convolutional neural network (CNN) training and inference in artificial intelligence and proposes to implement the process of CNN training and inference by using high-performance heterogeneous architecture (HA) devices with field programmable gate array (FPGA) as the core. Numerous repeated multiplication and accumulation operations in the process of CNN training and inference have been implemented by programmable logic (PL), which significantly improves the speed of CNN training and inference and reduces the overall power consumption, thus providing a modern implementation method for neural networks in an application field that is sensitive to power, cost, and footprint. First, based on the data stream containing the training and inference process of the CNN, this study investigates methods to merge the training and inference data streams. Secondly, high-level language was used to describe the merged data stream structure, and a high-level description was converted to a hardware register transfer level (RTL) description by the high-level synthesis tool (HLS), and the intellectual property (IP) core was generated. The PS was used for overall control, data preprocessing, and result analysis, and it was then connected to the IP core via an on-chip AXI bus interface in the HA device. Finally, the integrated implementation method was tested and validated with the Xilinx HA device, and the MNIST handwritten digit validation set was used in the tests. According to the test results, compared with using a GPU, the model trained in the HA device PL achieves the same convergence rate with only 78.04 percent training time. With a processing time of only 3.31 ms and 0.65 ms for a single frame image, an average recognition accuracy of 95.697%, and an overall power consumption of only 3.22 W @ 100 MHz, the two convolutional neural networks mentioned in this paper are suitable for deployment in lightweight domains with limited power consumption.

Rapid Prototyping of Image Contrast Enhancement Hardware Accelerator on FPGAs Using High-Level Synthesis Tools

Rapid prototyping tools have become essential in the race to market. In this work, we have explored employing rapid prototyping approach to develop an intellectual property core for real-time contrast enhancement which is a commonly employed image processing task. Specifically, the task involves real-time contrast enhancement of video frames, which is used to repair washed out (overexposed) or darkened (underexposed) appearance. Such scenario is frequently encountered in video footage captured underwater. Since the imaging conditions are not known a priori, the lower and upper limits of the dynamic range of acquired luminance values need to be adaptively determined and mapped to the full range permitted by the allocated bitwidth so that the processed image has a high-contrast appearance. This paper describes a hardware implementation of this operation using contrast stretching algorithm with the help of Simulink high-level synthesis tool using rapid prototyping paradigm. The developed model can be directly used as a drop-in module in larger computer vision systems to enhance Simulink computer vision toolbox capabilities, which does not support this operation for direct FPGA implementation yet. The synthesized core consumes less than 1% of total FPGA slice logic resources while dissipating only 7 mW dynamic power. To this end, look-up table has been employed to implement the division operator which otherwise requires exorbitantly large number of logic resources. Moreover, an online algorithm has been proposed which avoids multiple memory accesses. The hardware module has been tested in a real-time video processing scenario at 100 MHz clock rate and depicts functional accuracy at par with the software while consuming lower logic resources than competitive designs. These results demonstrate that the appropriate use of modern rapid prototyping tools can be highly effective in reducing the development time without compromising the functional accuracy and resource utilization.

A Gate-Level Information Leakage Detection Framework of Sequential Circuit Using Z3

Hardware intellectual property (IP) cores from untrusted vendors are widely used, raising security concerns for system designers. Although formal methods provide powerful solutions for detecting malicious behaviors in hardware, the participation of manual work prevents the methods from reaching practical applications. For example, Information Flow Tracking (IFT) represents a powerful approach to preventing leakage of sensitive information. However, existing IFT solutions either introduce hardware overheads or lack practical automatic working procedures, especially for hardware sequential logic. To alleviate these challenges, we propose a framework that fully automates information leakage detection at the gate level of hardware. This framework introduces Z3, an SMT solver, to automatically check the violation of confidentiality. On the other hand, an automatic tool is developed to remove the manual workload further. In this tool, the gate level hardware is converted to the formal model firstly, and the integrity of the model is assessed. Along with the model converting step, the property for leakage detection is generated as well. The proposed solution is tested on 25 gate-level netlist benchmarks, where sequential designs are included to validate the effectiveness. As a result, Trojans leaking information from circuit outputs can be automatically detected. The measured time consumption of the entire working procedure validates the efficiency of the proposed approach.

Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores

Reusable hardware intellectual property (IP) cores play a significant role in the modern system on chip (SoC) designs. However, raging threats of IP piracy and IP ownership infringement sabotage revenue and reputation of genuine IP vendors. This paper presents a novel quadruple phase watermarking for securing hardware IP cores during high level synthesis (HLS). The proposed approach introduces several novelties: graph partitioning, encoding tree, and eightfold mapping to generate a robust watermarking signature. Further, embedding signature during four phases of HLS viz. scheduling, register binding, resource binding and interconnect binding leads to a high-quality watermark. The proposed results indicate multiple times lower Pc and higher tamper tolerance than previous approaches, at negligible design cost overhead. We achieved improvements in Pc and tamper tolerance up to 1018 and 1052 times respectively than related works. Finally, security and design cost tradeoff for various signature strengths is presented.

Design considerations for hardware implementation of nanoseconds time synchronization low-cost system based on precise time protocol

Precise time synchronization is the key for coordinating every node of the distributed system to complete tasks. The widespread use of Field Programmable Gate Array (FPGA) in distributed nodes has a positive effect on improving time synchronization accuracy. Although the use of FPGA could significantly improve time synchronization accuracy, there is not a universal design guideline. This work has analyzed and summarized three factors that should be considered when building a low-cost clock synchronization system using FPGA: where the timestamp should be generated, the calculation and correction of time offset, and how to handle Precise Time Protocol (PTP) messages. Based on these design considerations, the time synchronization system intellectual property (IP) core was constructed. The synchronization accuracy experiments have been performed on Zynq system-on-chip (SoC) evaluation boards of different architectures. The experimental results demonstrated that the time synchronization system constructed in this article could achieve nanoseconds accuracy.

Designing an Arduino Board-based Electronic Device Driven by GRBL Gru to Operate the Mini PCB Printing Machine

A compact integrated circuit is an intellectual property core at the heart of the decades of embedded devices on embedded systems. Using a microcontroller-based electronic module manufactured as desired or direct service of the board of Arduino as a control system for many purposes has become a certainty. Defining the problem formulations is related to the manufacture, assembly of the mechanical apparatus, and integrated wiring of several electronic modules. The acquisition of research contributions is expected to get the miniature embodiment of the physical machine equipped with a user program and perform the machine driver. The research methods consist of several steps to carry out each research objective. The miniature embodiment is carried out through (i) manufacturing and assembling to obtain the physical machine, (ii) integrating the electronic modules and all components and support systems by wiring to form an embedded system as a mini-PCB printing machine, and (iii) making a program structure based on Arduino IDE. Performing the machine driving mechanism is operating tests of calibration and moving on the axes of X, Y, and Z. Concluding based on the implementation process, testing, and analysis are carried out that the stages for performing the Mini PCB Printing Machine assisted by Arduino board with driven by GRBL Gru can be realized according to the initial design of hardware and software design.

Palmprint Biometric Versus Encrypted Hash Based Digital Signature for Securing DSP Cores Used in CE Systems

In the prior articles of reusable intellectual property (IP) core, different facets of their threat models and defence mechanisms against IP Trojan and IP piracy have been presented. This article provides novel comparative perspective between the two security techniques viz. palmprint biometric based approach and encrypted hash-based digital signature approach for IP cores, integrated in Consumer Electronics systems. These reusable IP cores such as finite impulse response filter used in audio devices, HD TVs, etc., discrete cosine transform core used in audio/image/video/compression, fast Fourier transform used in digital video broadcasting and JPEG-CODEC used in image/video compression of camera systems can be secured using the two security methodologies discussed in this article. These both approaches enable detective control against important security threats such as IP piracy, fraudulent claim of IP ownership, overproduction, and IP counterfeiting. The article therefore contributes the following: 1) security comparison of security techniques on digital signal processing IP cores in terms of probability of coincidence and tamper tolerance, 2) comparison between two security techniques in terms of its properties, 3) end to end demonstration of the palmprint biometric security approach, and 4) design flow of the encrypted hash-based digital signature approach.

Accurate Power Estimation Identity for DSP Blocks Targeted to FPGAs

Nowadays, the main challenge in front of system designers is to design power-efficient systems with reduced design turnaround time. It can be achieved in two ways, firstly, utilize off-shelf components (Intellectual Property cores) along with user-defined IPs. Secondly, estimate the power at an early stage of the design cycle. Therefore, this paper represents the power estimation of Cascaded and Non-Cascaded DSP blocks based on IP modeling. The DSP blocks are designed using a blend of embedded and user-defined IP cores. Curve-fitting and regression-based models for power evaluation have been created for each IP core. The power of the complete DSP block is estimated using identity projected by Elleouet et al. by incorporating the power values of each IP core obtained from the regression-based models. The models have been validated for accuracy using the power values gained from the commercial tool (Vivado design suite (2014.2)). From the analysis, it has been found that the identity is providing inaccurate results for cascaded DSP blocks. Therefore, in this work, a new identity has been proposed that has been estimating the power of the cascaded systems accurately and also in alignment with the results of a commercial tool.

Low-Power Low-Area Near-Lossless Image Compressor for Wireless Capsule Endoscopy

The paper presents the concept of a low-power, low-area, near-lossless image compressor for resource-constrained devices such as wireless capsule endoscopy (WCE). The compressor directly processes the raw data from the Bayer Color Filter Array (CFA) imager to avoid the high cost of color interpolation. To improve the efficiency of the compressor in terms of energy consumption, silicon area and compression ratio, the main part of the compressor, i.e., the entropy encoder, uses the existing correlations between the color components of a captured CFA image. The proposed image compressor requires only 12.4% of the memory needed by other high-quality CFA compressors based on the JPEG-LS standard. Despite this significant reduction in memory size, the proposed image compressor outperforms other state-of-the-art coding schemes on capsule endoscopy images. At the same time, it offers only slightly lower performance on standard test images. The proposed image compressor has been implemented as an intellectual property (IP) core using two different low-cost CMOS processes. The design, implemented in UMC 180 nm CMOS process, requires a very low silicon area (534 times 426 upmu m^{2}) and consumes very low energy (22 upmu J per a single 512 times 512 image frame). Even higher energy efficiency (12 upmu J per the same image frame) has the IP core implemented in the TSMC 130 nm CMOS process. Both of the selected technologies are low-cost and well-suited to implement a radio frequency transmitter and a low-power successive approximation register analog-to-digital converter in addition to the compressor to provide a cost-effective System on Chip for resource-constrained devices like WCE or wireless camera sensor network.

Secured Convolutional Layer IP Core in Convolutional Neural Network Using Facial Biometric

This paper presents a novel methodology to design a secured custom reusable intellectual property (IP) core for the convolutional layer of convolutional neural network (CNN). Since the reusable IP cores used in system-on-chips (SoCs) of consumer electronics (CE) systems are susceptible to the hardware threat of IP counterfeiting. Therefore, this paper also presents the security of the proposed convolutional layer reusable IP core against the threat of IP counterfeiting using facial biometrics. This enables the integration of secured reusable IP cores in the SoCs of CE systems, thereby ensuring the safety of end consumers. In the proposed approach, the convolutional layer IP core is designed through high-level synthesis (HLS) process and secured by embedding secret biometric security information into the design during register allocation phase of the HLS process. The qualitative and quantitative analysis of the proposed approach exhibits significantly lower probability of coincidence (Pc) (up to 47% less) and higher tamper tolerance (1.93E+25) than recent approaches. Further, it offers robust security with zero design overhead.

Digitally Assisted Mixed-Signal Circuit Security

The design and manufacturing steps of a chip typically involve several parties. For example, a chip may comprise several third-party intellectual property (IP) cores and the integrated circuit (IC) fabrication may be outsourced to a third-party foundry. IP cores and ICs are shared with potentially untrusted third parties and, as a result, are subject to piracy attacks. Even more, any legally purchased chip may be reverse engineered to retrieve the design down to transistor level and, thereby, it is also subject to piracy attacks. In this article, we propose <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MixLock</i> , an anti-piracy countermeasure for mixed-signal IP cores and ICs. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MixLock</i> protection is based on inserting a lock mechanism into the design such that correct functionality is established only after applying a key which is the designer’s secret. The lock mechanism acts on the mixed-signal performances by leveraging logic locking of the digital part. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MixLock</i> presents several key attributes. It is generally applicable, it is nonintrusive to the sensitive analog section, it incurs no performance penalty and has very low area and power overheads, it is fully automated, and it is capable of co-optimizing security in both the analog and digital domains. We demonstrate <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MixLock</i> on a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Sigma \Delta $ </tex-math></inline-formula> analog-to-digital converter (ADC) using hardware measurements and an audio demonstrator.

A High-Throughput Vernier Time-to-Digital Converter on FPGAs with Improved Resolution Using a Bi-Time Interpolation Scheme

A novel ring oscillator-based Vernier-type time interpolation method, known as the fine-timestamp maker, is proposed for field programmable gate array (FPGA)-based time-to-digital converters (TDCs). This method determines lower measurement dead time and improves resolution by using a bi-time interpolation scheme, first presented in this paper. Additionally, a group of cascaded delay units are packaged as an intellectual property core (DU-IP) to form a ring delay line and to adjust its length via the engineering change order (ECO) tool, which makes the adjustment of the ring oscillator’s frequency more linear and less position dependent. A prototype TDC was implemented on a Kintex-7 FPGA. The experimental results demonstrate that a single TDC channel only consumes 35 DFFs, 31 LUTs, and 16 CARRY4 logics after specific adjustment. The results, with a time resolution of 20 ps, dead time of 58 ns, and a root-mean-square error of 15–20 ps, show a significant performance improvement compared to traditional Vernier-type TDCs.

Multicriteria Deming Regressive African Buffalo Optimized Mapping for 3D NoC Architecture Design

Purpose. Networks-on-Chip (NoC) is a network-based communication between operating cores and intellectual property (IP) cores integrated on the same chip. An efficient design of NoC ensures high-speed data transfer and minimum essential connections in large-scale multicore, low power applications. Design/methodology/approach. A unique technique called Multicriteria Deming Regressive African Buffalo Optimized Mapping Weighted Directive Graph Theory (MDRABOMWDGT) is introduced for an efficient Network-on-Chip architecture design. The main aim of the proposed technique is to find efficient operating cores integrated on the chip with minimum time. Initially, a set of IP cores are listed with their connections from the benchmark dataset. Then Multicriteria Deming Regressive African Buffalo Optimization is applied to the topology for mapping strategy on 3D NoC, with communication metrics such as throughput, latency, and computation time. The optimization technique initializes the population of cores in search space. For each core in the network, communication metrics are measured; then Deming regression is applied to analyze multicriteria functions for minimizing computation time. Further, fitness is measured to get an optimal IP core for improving the performance of mapping in 3D NoC. Findings. Comprehensive experimental evaluation is conducted using a benchmark dataset, communication metrics are measured, and results show significant improvement in performance with respect to energy parameters compared to state-of-the-art works. Originality/value. The mapping strategy for 3D NOC is developed and the results are compared with the state-of-the-art techniques.

Digital Watermarking for Detecting Malicious Intellectual Property Cores in NoC Architectures

System-on-chip (SoC) developers utilize intellectual property (IP) cores from third-party vendors due to increasing design complexity, cost, as well as time-to-market constraints. A typical SoC consists of a wide variety of IP cores [such as processor, memory, controller, and field-programmable gate array (FPGA)] that interact using a network-on-chip (NoC). This global trend of designing SoCs using third-party IPs raises serious concerns about security vulnerabilities. Since NoC facilitates communication between all IPs in an SoC, NoC is the ideal place for any hardware Trojans to hide and launch a plethora of attacks. Due to the resource-constrained nature of SoCs, developing security solutions against such attacks is a major challenge. In particular, in an eavesdropping attack, a Trojan-infected router copies packets transferred through the NoC and reroutes the duplicated packets to an accompanying malicious application running on another IP in an attempt to extract confidential information. While authenticated encryption can thwart such attacks, it incurs unacceptable overhead in resource-constrained SoCs. In this article, we propose a lightweight alternative defense based on digital watermarking techniques. We develop theoretical models to provide security guarantees. Experiments using realistic SoC models and diverse applications demonstrate that our approach can significantly outperform state-of-the-art methods.