PSO based exploration of multi-phase encryption based secured image processing filter hardware IP core datapath during high level synthesis

Abstract

Image processing filter intellectual property (IP) cores perform different critical operations on images such as blurring, sharpening, edge detection, etc., which are essential functions in several multimedia systems. The design process of the image filter cores as a dedicated IP needs to consider multiple objectives such as area, delay, and security against various hardware threats such as IP piracy (counterfeiting and cloning) and fraudulent claim of IP ownership during design space exploration (DSE) in high level synthesis (HLS). This paper presents the following novelties: (a) particle swarm optimization (PSO) driven exploration of secured image processing filter IP core datapath architecture during HLS capable of providing detective control against IP piracy threat (b) the proposed approach incorporates embedding of covert security constraints based on the proposed multi-phase encryption algorithm during performing area-delay tradeoff via PSO based DSE. The proposed approach achieves stronger security in terms of digital proof of > 2X and higher tamper tolerance as well as attains a lower design cost of 56.92% in terms of area-delay than recent approaches. The proposed approach also achieves optimal solution as evident from the optimality analysis performed on metrics such as generational distance, spacing, spreading, and weighted sum.