Abstract

The digital signal processing (DSP)-based intellectual property (IP) cores are massively being integrated in the modern system-on-chips (SoCs) developed for consumer electronic systems. The reason behind the thriving of DSP-based chips in the consumer electronics market is the vital role of DSP algorithms to perform functions such as filtering (de-noising), data compression-decompression, encoding-decoding etc. However the journey of a DSP-based IP core from its algorithmic form to an IP block within an end SoC is susceptible to hardware threats such as possible hardware Trojan (malicious logic) insertion, IP misuse and fraud claim. This is due to the involvement of more than one design house (fabless and foundry) in the integrated circuit (IC) design chain. For example: (i) Components or IP blocks used in the high-level synthesis (HLS) design process may be Trojan infected as they are supplied by a distinct third-party IP (3PIP) vendor. Thus integrated malicious components in the chip design may cause failure during critical operations. (ii) An IP core design of a genuine vendor may be illegally misused by an adversary in an untrustworthy design house or foundry. These threats of Trojan insertion and IP misuse can be handled during the HLS design process of an IP core. However, employing security techniques may result in design overhead in terms of additional hardware area and latency. This challenge can be addressed by integrating a particle swarm optimization (PSO, a nature-inspired algorithm)-based design space exploration (DSE) process with the HLS design process to explore a low-cost security solution. This chapter discusses (i) a PSO-DSE-driven low-cost Trojan security-aware HLS technique to enable the detection of hidden Trojan in the design components and (ii) a PSO-DSE-driven low-cost watermark security-aware HLS technique to enable the detection of IP piracy and nullification of fraud claim of IP ownership.

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