Intellectual Property Blocks Research Articles

FPGA-Based CNN for Eye Detection in an Iris Recognition at a Distance System

Neural networks are the state-of-the-art solution to image-processing tasks. Some of these neural networks are relatively simple, but the popular convolutional neural networks (CNNs) can consist of hundreds of layers. Unfortunately, the excellent recognition accuracy of CNNs comes at the cost of very high computational complexity, and one of the current challenges is managing the power, delay and physical size limitations of hardware solutions dedicated to accelerating their inference process. In this paper, we describe the embedding of an eye detection system on a Zynq XCZU4EV UltraScale+ multiprocessor system-on-chip (MPSoC). This eye detector is used in the application framework of a remote iris recognition system, which requires high resolution images captured at high speed as input. Given the high rate of eye regions detected per second, it is also important that the detector only provides as output images eyes that are in focus, discarding all those seriously affected by defocus blur. In this proposal, the network will be trained only with correctly focused eye images to assess whether it can differentiate this pattern from that associated with the out-of-focus eye image. Exploiting the neural network’s advantage of being able to work with multi-channel input, the inputs to the CNN will be the grey level image and a high-pass filtered version, typically used to determine whether the iris is in focus or not. The complete system synthetises other cores and implements CNN using the so-called Deep Learning Processor Unit (DPU), the intellectual property (IP) block released by AMD/Xilinx. Compared to previous hardware designs for implementing FPGA-based CNNs, the DPU IP supports extensive deep learning core functions, and developers can leverage DPUs to conveniently accelerate CNN inference. Experimental validation has been successfully addressed in a real-world scenario working with walking subjects, demonstrating that it is possible to detect only eye images that are in focus. This prototype module includes a CMOS digital image sensor that provides 16 Mpixel images, and outputs a stream of detected eyes as 640 × 480 images. The module correctly discards up to 95% of the eyes present in the input images as not being correctly focused.

Hardware-Supported Patching of Security Bugs in Hardware IP Blocks

To satisfy various design requirements and application needs, designers integrate multiple intellectual property blocks (IPs) to produce a system on chip (SoC). For improved survivability, designers should be able to patch the SoC to mitigate potential security issues arising from hardware IPs; for increased flexibility, we propose adding programmable hardware-based support for monitoring and bug mitigation. However, it is a challenge to decide how much additional cost a designer should expend up front to deal with unknown, future issues. We propose an approach that guides designers toward maximizing the benefits of adding “patchability” to various IPs in the system, given a target resource overhead. We frame the design problem as an integer quadratic program and show that our approach achieves superior patchability compared to the naïve and baseline approaches for a given cost limit. Experimental results show that when we set a cost limit of 2% field-programmable gate array adaptive logic module usage, our solution can generate a viable patching infrastructure with six patching blocks offering patches for seven different services in our case study.

Digital-to-Analog Hardware Trojan Attacks

We propose a Hardware Trojan (HT) attack for analog circuits with its key characteristic being that it cannot be prevented or detected in the analog domain. The HT attack works in the context of Systems-on-Chip (SoCs) comprising both digital and analog Intellectual Property (IP) blocks. The attacker could be either the SoC integrator or the foundry. More specifically, the HT trigger is placed inside a dense digital IP block where it can be effectively hidden, whereas the HT payload is in the form of a digital pattern transported via the test bus or generated within the test bus, reaching the Design-for-Test (DfT) or programmability interface of the victim analog IP with the test bus. The HT payload unexpectedly activates the DfT and sets the victim analog IP into some possibly partial and undocumented test mode or changes the nominal programmability. The HT payload can be designed to result in performance degradation or complete malfunction, i.e., denial of service. We demonstrate this HT attack scenario on two analog IPs, namely a low-dropout (LDO) regulator using simulation and an RF receiver using hardware measurements.

An Efficient HW/SW Design for Text Extraction from Complex Color Image

In the context of constructing an embedded system to help visually impaired people to interpret text, in this paper, an efficient High-level synthesis (HLS) Hardware/Software (HW/SW) design for text extraction using the Gamma Correction Method (GCM) is proposed. Indeed, the GCM is a common method used to extract text from a complex color image and video. The purpose of this work is to study the complexity of the GCM method on Xilinx ZCU102 FPGA board and to propose a HW implementation as Intellectual Property (IP) block of the critical blocks in this method using HLS flow with taking account the quality of the text extraction. This IP is integrated and connected to the ARM Cortex-A53 as coprocessor in HW/SW codesign context. The experimental results show that the HLS HW/SW implementation of the GCM method on ZCU102 FPGA board allows a reduction in processing time by about 89% compared to the SW implementation. This result is given for the same potency and strength of SW implementation for the text extraction.

A State-Space-Based Method to Model Vccin Feedthrough Noise in Microprocessors With Fully Integrated Voltage Regulators

Modern high-performance server microprocessors need to integrate multiple intellectual property (IP) blocks in a single chip to achieve higher performance. Due to the diverse supply voltage requirements of these IP blocks, their supply voltages are generated locally on the chip using fully integrated voltage regulators (FIVRs). FIVR is designed using on-chip power bridges, bridge drivers, control circuits, on-chip metal–insulator–metal (MIM) capacitors, package inductors, and package power planes. The input power supply (Vccin) of all the FIVRs is shared to minimize the platform cost and is generated using a voltage regulator module (VRM) on the motherboard. The noise coupling between FIVRs due to the common input supply is referred to as the Vccin feedthrough noise. The existing method of modeling the Vccin feedthrough noise is based on circuit simulation. Circuit models are highly complex as different components such as the FIVR power bridges, bridge drivers, MIM capacitors, package inductors, package power planes, and the Vccin network need to be modeled. Convergence issues are very frequent in full chip circuit simulations and it typically takes many iterations. Hence design optimization is difficult to carry out using circuit simulations. In this article, a state-space-based time-domain method is proposed to model the Vccin feedthrough noise based on G-parameters and S-parameters of the FIVR and the Vccin network. The state-space models are generated using the vector-fitting algorithm. The proposed method simplifies the construction of the Vccin feedthrough models and improves the convergence time.

ЗАХИСТ БЛОКІВ ІНТЕЛЕКТУАЛЬНОЇ ВЛАСНОСТІ У СПЕЦІАЛІЗОВАНИХ КОМП’ЮТЕРНИХ ЗАСОБАХ НА БАЗІ ПЛІС

The current evolutionary stage of the microchips’ architecture of programmable logic does precondition not only a rationale for but also desirability of its utilisation when developing specialised computer means or the combinatory part of devices of computing machines. The increase in complexity of digital computational devices, especially in the critical usage’ computer systems, dramas and focuses the attention of developers and OEMs of FPGA to the occurrence of events related to the devices’ correct operation’ interruption, that may be caused both by external factors and intrusion. If events that are caused by negative external impacts such as a Single-Event Effect, may be related to the transition to new technological norms of the semiconductor products manufacturing, e.g. FPGA microchips, then any intrusions to the devices’ operation have anthropological origins. Widespread use of FPGA to implement the specialised computer means prompts the use of the intellectual property blocks (intellectual property core, IP-core) since to create certain samples of hardware the broad functional capabilities have to be implemented, which is effectuated by the IP. Such an approach enables materialisation of the substantial feature set in a specialised device, overcome the complexities in the devices’ development and narrow down time-frames. A part of an overview of the efficient IP cores protection, being an important and complex task, is exemplified in the paper. Different approaches and methods are outlined for such protection organisation. Examples are given of the examples of the additional structures’ usage, complementary to ciphering and authentication, that prohibit unauthorised access.

Toward Hardware-Based IP Vulnerability Detection and Post-Deployment Patching in Systems-on-Chip

System integrators create heterogeneous systems-on-chip (SoCs) by integrating numerous third-party intellectual property blocks (3PIPs) to achieve application-specific design goals. With increasing intellectual property (IP) complexity, 3PIPs can suffer from hardware bugs or they can inadvertently introduce other software-exploitable security threats to the SoC. To ensure the ongoing survivability of new SoCs, we need infrastructure for patching newly discovered IP issues after an SoC has been deployed. To address the increasing risks from 3PIPs, we explore the feasibility and limitations of implementing monitoring and mitigation capabilities in hardware. Our proposed monitoring and mitigation patch (MoP) blocks provide a defensive foundation against critical IP-centric issues, focusing on situations where a system integrator only has interface-level visibility of 3PIP designs. The MoPs are distributed throughout the SoC to monitor and mitigate issues directly in hardware and transparently for potentially compromised software-the MoPs are resilient against run-time compromised software and firmware. We ensure that these monitors are reconfigurable after deployment by implementing them using embedded-FPGAs or as a reprogrammable, fixed-design module. We perform a case study of numerous IP-types and model a selection of security-relevant issues and bugs in the IPs, exploring the relative complexity and potential resource overhead. Our study shows the utility of our proposed approach, with MoP blocks requiring less than ~1.5% of the adaptive logic modules (ALMs) in a Cyclone V FPGA for interface monitoring and issue mitigation per IP.

Revealing Cluster Hierarchy in Gate-level ICs Using Block Diagrams and Cluster Estimates of Circuit Embeddings

Contemporary integrated circuits (ICs) are increasingly being constructed using intellectual property blocks (IPs) obtained from third parties in a globalized supply chain. The increased vulnerability to adversarial changes during this untrusted supply chain raises concerns about the integrity of the end product. The difference in the levels of abstraction between the initial specification and the final available circuit design poses a challenge for analyzing the final circuit for malicious insertions. Reverse engineering presents one way to help reduce the difficulty of circuit analysis and inspection. In this work, we provide a framework that given (i) a gate-level netlist of a design and (ii) a block diagram for the design with relative sizes of the blocks, outputs a matching between the partitions of the circuit and blocks in the block diagram. We first compute a geometric embedding for each node in the circuit and then apply a clustering algorithm on the embedding features to obtain circuit partitions. Each partition is then mapped to the high-level blocks in the block diagram. These partitions can then be further analyzed for malicious insertions with much reduced complexity in comparison with the full chip. We tested our algorithm on different designs with varying sizes to evaluate the efficacy of algorithm, including the open-source processor OpenSparc T1, and showed that we can successfully match over 90% of gates to their corresponding blocks.

Error Detection and Correction in SRAM Emulated TCAMs

Ternary content addressable memories (TCAMs) are widely used in network devices to implement packet classification. They are used, for example, for packet forwarding, for security, and to implement software-defined networks (SDNs). TCAMs are commonly implemented as standalone devices or as an intellectual property block that is integrated on networking application-specific integrated circuits. On the other hand, field-programmable gate arrays (FPGAs) do not include TCAM blocks. However, the flexibility of FPGAs makes them attractive for SDN implementations, and most FPGA vendors provide development kits for SDN. Those need to support TCAM functionality and, therefore, there is a need to emulate TCAMs using the logic blocks available in the FPGA. In recent years, a number of schemes to emulate TCAMs on FPGAs have been proposed. Some of them take advantage of the large number of memory blocks available inside modern FPGAs to use them to implement TCAMs. A problem when using memories is that they can be affected by soft errors that corrupt the stored bits. The memories can be protected with a parity check to detect errors or with an error correction code to correct them, but this requires additional memory bits per word. In this brief, the protection of the memories used to emulate TCAMs is considered. In particular, it is shown that by exploiting the fact that only a subset of the possible memory contents are valid, most single-bit errors can be corrected when the memories are protected with a parity bit.

Design of a Radiation Hardened Power-ON-Reset

In this paper, the design of a power-ON-reset intellectual property (IP) block for the RD53 collaboration, a radiation hardening by design circuit to withstand the High-Luminosity Large Hadron Collider tracker radiation environment, is presented. In this environment, the performance of the IP block under radiation must be ensured for a total ionizing dose up to 500 Mrad and possible ions interaction for a linear energy transfer of 15 MeV/cm2/mg. To verify the radiation hardness of the presented circuit, an automatic single-event effect sensitivity tool (Analog Fault Tolerant University of Seville Hardware Debugging System) has been used to perform a complete analysis over it, and also several experiments have been performed to test the designed blocks and obtain the final IP qualification.

A Functionality-Based Runtime Relocation System for Circuits on Heterogeneous FPGAs

Runtime relocation of circuits on field-programmable gate arrays (FPGAs) has been proposed for achieving many desirable features including fault tolerance, defragmentation, and system load balancing. However, the changes in the architectural composition of FPGAs have made relocation more challenging mainly because FPGAs have become more heterogeneous. Previous and state-of-the-art circuit relocation systems on FPGAs have relied only on direct bitstream relocation which requires the source and destination resource layouts to be the same, as well as access to the design bitstream for manipulation. Hence, their efficiency on modern heterogeneous chips greatly reduces, and mostly cannot be applied to encrypted bitstreams of intellectual property blocks. In this brief, we present a circuit relocator which augments direct bitstream relocation with a functionality-based relocation scheme. We demonstrate the feasibility of the proposed technique using a CORDIC application and show that an average of over 2.6-fold increase in the number of relocations can be obtained compared to only direct bitstream relocation at the expense of a small memory overhead and manageable relocation time for this case study.

Graph-Grammar-Based IP-Integration (GRIP)—An EDA Tool for Software-Defined SoCs

In modern system-on-chip (SoC) designs, IP-reuse is considered a driving force to increase productivity. To support various designs, a huge amount of Intellectual Property (IP) hardware blocks have been developed. The integration of those IPs into an SoC may require significant effort—up to days or weeks depending on experience and complexity. This article presents a novel approach to significantly reduce the design effort to bring-up a working SoC design by automatic IP integration as part of a library-based Software-defined SoC flow. In detail, the IP-supplier prepares a HW-accelerated software library (HASL) for the SoC architect, who wants to use the IP in an SoC design. As a key point of our approach, integration knowledge is encoded in the library as a set of integration rules. These rules are defined in the machine-readable standardized IP-XACT format by the IP supplier, who has a good knowledge of the IP’s hardware details. The library preparation step on the IP supplier’s side is also partly automated in the proposed flow, including a partial generation of configurable HW drivers, schedulers, and the software library functions. For the SoC architect, we have developed the graph-grammar-based IP-integration (GRIP) tool. The software application is developed using the functions supplied in the HASL. According to the calls to the HASL functions, the GRIP tool automatically integrates IP-blocks using the rule information supplied with the library and runs a full Design Space Exploration. For this, the SoC architecture and rules are transformed into the graph domain to apply graph rewriting methods. The GRIP tool is model-driven and based on the Eclipse Modeling Framework. With code generation techniques, SoC candidate architectures can be transformed to hardware descriptions for the target platform. The HW/SW interfaces between SW library functions and IP blocks can be automatically generated for bare-metal or Linux-based applications. The approach is demonstrated with two case-studies on the Xilinx Zynq-based ZedBoard evaluation board using a HASL for computer vision. It can yield 10×-150× performance improvement for the bare-metal application versions and 4×--7× performance improvement for the Linux-based application versions, when executed on an optimized HW-accelerated SoC architecture compared to a non HW-accelerated SoC. The effort for IP integration is comparable to using a software library, hence, providing a significant advantage over a manual IP integration.

Clock Network Optimization With Multibit Flip-Flop Generation Considering Multicorner Multimode Timing Constraint

Clock network should be optimized to reduce clock power dissipation. The power efficient clock network can be constructed by multibit flip-flop generation and gated clock tree aware flip-flop clumping to pull flip-flops close to the same integrated clock gating cell. It is capable of providing an attractive solution to reduce clock power. This paper considers multicorner and multimode timing constraints for the two combined approach. This proposed method is applied to five industrial digital intellectual property blocks of state-of-the-art mobile system-on-a-chip fabricated in 14-nm CMOS process. Experimental results show that MBFF generation algorithm achieves 22% clock power reduction. Applying a gated clock tree aware flip-flop clumping on top of the MBFF generation further reduces the power to around 32%.

System-on-Chip Platform Security Assurance: Architecture and Validation

Modern system-on-chip (SoC) designs include a wide variety of highly sensitive assets which must be protected from unauthorized access. A significant aspect of SoC design involves exploration, analysis, and evaluation of resiliency mechanisms against attacks to such assets. These attacks may arise from a number of sources, including malicious intellectualproperty blocks (IPs) in the hardware, malicious or vulnerable firmware and software, insecure communication of the system with other devices, and side-channel vulnerabilities through power and performance profiles. Countermeasures for these attacks are equally diverse, which include architecture, design, implementation, and validation-based protection. In this paper, we provide a comprehensive overview of the security infrastructure in modern SoC designs, including both resiliency techniques and their validation paradigms at presilicon and postsilicon stages. We identify gaps in current resiliency and analysis architectures and propose design and validation solutions to address them. Finally, we provide industry perspectives on the role and impact of current practices on SoC security, and discuss some emerging trends in this important area.

A novel heuristic algorithm for IP block mapping onto mesh-based networks-on-chip

With advancement in the nanometer era, more and more intellectual property (IP) blocks can be integrated on a single die. Network-on-chip (NoC) has emerged as a viable alternative to unplug the communication bottleneck in system-on-chip. In the NoC synthesis flow, IP block mapping problem is one of the holistic research problems, which aims to minimize the overall communication cost or power consumption of the network. Since mesh is a well-accepted topology, we focus on IP mapping problem onto mesh-based NoCs in this paper. The IP mapping problem is proven to be NP-hard. No exact algorithm is expected to solve it in the polynomial time, and considerable computation time is required for even small-scale instances. In this paper, we analyze the symmetry character in mesh and propose an adaptive memetic algorithm (AMA) to solve the application mapping problem. The novel AMA method integrates both global and local optimization techniques, which contributes to the effectiveness and efficiency of the algorithm. Experiments have been carried out under both real application and synthetic benchmarks. Experimental results indicate that the proposed AMA outperforms the existing heuristics (CastNet and genetic algorithm) in the aspects of solution quality and power consumption. Within acceptable time limit, AMA could obtain optimal or suboptimal solutions when compared with the exact algorithm.

A Formal Approach to Incremental Converter Synthesis for System-on-Chip Design

A system-on-chip (SoC) contains numerous intellectual property blocks, or IPs. Protocol mismatches between IPs may affect the system-level functionality of the SoC. Mismatches are addressed by introducing converters to control inter-IP interactions. Current approaches towards converter generation find limited practical application as they use restrictive models, lack formal rigour, handle a small subset of commonly encountered mismatches, and/or are not scalable. We propose a formal technique for SoC design using incremental converter synthesis . The proposed formulation provides precise models for protocols and requirements, and provides a scalable algorithm that allows adding multiple components and requirements to an SoC incrementally. We prove that the technique is sound and complete. Experimental results obtained using real-life AMBA benchmarks show the scalability and wide range of mismatches handled by our approach.

Application of IP-Based Analog Platforms in the Design of Neuromimetic Integrated Circuits

Reuse methodologies are now widely used to design digital circuits. They are based on the concept of intellectual property (IP), or virtual block of computing, characterized by a behavioral model, synthesizable or not. The design reuse for analog integrated systems is much less natural and less standardized. This paper addresses the issue of an analog design flow based on reuse, focusing on three key issues: the formal content of the IP block, the design of a reusable analog IP, and the organization of a design flow centered on an IP library. After a conceptual overview, this paper presents the methodological principles and details examples with a tutorial intention. The objective is to guide the designer involved in the process of developing analog IPs and corresponding design flow. This method is inspired by platform-based design and adapted here on an original case study: the design of full-custom neuromimetic integrated circuits, built from specific analog computational blocks. The development of reusable IPs represents an additional effort, mainly for behavioral modeling and characterization. Nevertheless, the steps illustrated in this case study show that the extra time provides a definite advantage to future design projects.

A systematic approach to configurable functional verification of HW IP blocks at transaction level

With demand growing by the day, the complexity of electronic devices is constantly increasing. Since simulation is still the most used approach, functional verification has become one of the major bottlenecks in the design and verification flow.In this paper we propose a systematic approach to configurable functional verification of electronic devices. Based on a black box approach, it can be applied to any design where behavior can be expressed by a set of functions. It combines simulation- and assertion-based verification into a hybrid verification. The proposed specification-based coverage metric can be configured ranging from a very rapid to an exhaustive verification. The approach uses Transaction Level (TL) modeling to raise the abstraction level, providing faster verification. The results of the proposed design and verification flow, Intellectual Property (IP) and Test Bench (TB) are reusable.The approach is demonstrated on two case-studies; a video-processing IP block and universal serial bus host controller. The results consider both simulation times and TB generation times.

NoC based Efficient RTL Design and Verification of SoCWire BUS Protocol

System on Chip Wire (SoCWire) is a Network on Chip (NoC) based design that composed of intellectual property blocks (IP) and interconnects based on space wire standard, was successfully implemented in Venus Express Monitoring Camera (VMC) mission and proposed to implement in Solar Orbital mission in future. The efficient and accurate implementation of SoCWire is the main concern in this work. A solution for single bit error detection and correction with hamming code for 8 bit data has been proposed, so that the accuracy of the design is improved with cost of extra resources and we can save nearly 19.2 μs time that is required to link re-initialization also the speed of the design is improved compared to conventional Codec. For routing data of many codec from one node to many other nodes SoCWire Switch is implement with crossbar based switch for 8 ports and achieved maximum frequency 179.743 MHz and 5% device utilization can be saved compared to [1]. These functionality and design performance are achieved with coding level change in VHDL for SoCWire. The design is synthesized on Xilinx ISE 12.1. The Target FPGA is XCVLX-60 which belongs to Xilinx Virtex 4 QPro.

Implementation of Smart Sensor with Frequency To Digital Convertor For Flow Measurement Using FPGA

The realization of integrated frequency-based smart sensor for flow measurement requires a precise frequency to digital converter. A VHDLbased implementation of such converter for a royalty-free solution with 1 p pm resolution is reported. This work is part of a correlator under development to measure total flow of multiphase fluids. This intellectual property block can also be used with other frequency encoded transducers. The converter has been prototyped with a Xilinx TM XC3S500E Spartan3E FPGA, and has been tested up to 10MHz