ЗАХИСТ БЛОКІВ ІНТЕЛЕКТУАЛЬНОЇ ВЛАСНОСТІ У СПЕЦІАЛІЗОВАНИХ КОМП’ЮТЕРНИХ ЗАСОБАХ НА БАЗІ ПЛІС

Abstract

The current evolutionary stage of the microchips’ architecture of programmable logic does precondition not only a rationale for but also desirability of its utilisation when developing specialised computer means or the combinatory part of devices of computing machines. The increase in complexity of digital computational devices, especially in the critical usage’ computer systems, dramas and focuses the attention of developers and OEMs of FPGA to the occurrence of events related to the devices’ correct operation’ interruption, that may be caused both by external factors and intrusion. If events that are caused by negative external impacts such as a Single-Event Effect, may be related to the transition to new technological norms of the semiconductor products manufacturing, e.g. FPGA microchips, then any intrusions to the devices’ operation have anthropological origins. Widespread use of FPGA to implement the specialised computer means prompts the use of the intellectual property blocks (intellectual property core, IP-core) since to create certain samples of hardware the broad functional capabilities have to be implemented, which is effectuated by the IP. Such an approach enables materialisation of the substantial feature set in a specialised device, overcome the complexities in the devices’ development and narrow down time-frames. A part of an overview of the efficient IP cores protection, being an important and complex task, is exemplified in the paper. Different approaches and methods are outlined for such protection organisation. Examples are given of the examples of the additional structures’ usage, complementary to ciphering and authentication, that prohibit unauthorised access.