Secured design flow using palmprint biometrics, steganography, and PSO for DSP coprocessors

Abstract

Reusable intellectual property (IP) cores are widely used in all modern digital integrated circuits (ICs) in the form of application-specific processors or hardware accelerators. Reusable IP cores integrated in system-on-chip (SoC) platforms of integrated circuits and systems provide a powerful blend of yielding superior design productivity with reduced design cycle time. However, leveraging advantages of IP core require low-cost security against threats such as piracy and fraudulent claim of ownership. This chapter discusses the following aspects: (a) security-aware end-to-end high-level synthesis (HLS)-based design methodology using low-cost steganography technique for protecting IP cores used in digital ICs; (b) security-aware end-to-end HLS-based design methodology using low-cost biometric signature for protecting IP cores used in digital ICs; (c) secured RTL designs of reusable IP core embedding secret steganography mark and biometric signature respectively offering low overhead, strong robustness, and greater security in terms of lower probability of coincidence and higher tamper tolerance. Further, the chapter also discusses the achieved robustness of > 2× (i.e., stronger digital evidence as evident from the lower probability of coincidence) and lower design cost (~6.17%) than state-of-the-art approaches.