A State-Space-Based Method to Model Vccin Feedthrough Noise in Microprocessors With Fully Integrated Voltage Regulators

Abstract

Modern high-performance server microprocessors need to integrate multiple intellectual property (IP) blocks in a single chip to achieve higher performance. Due to the diverse supply voltage requirements of these IP blocks, their supply voltages are generated locally on the chip using fully integrated voltage regulators (FIVRs). FIVR is designed using on-chip power bridges, bridge drivers, control circuits, on-chip metal–insulator–metal (MIM) capacitors, package inductors, and package power planes. The input power supply (Vccin) of all the FIVRs is shared to minimize the platform cost and is generated using a voltage regulator module (VRM) on the motherboard. The noise coupling between FIVRs due to the common input supply is referred to as the Vccin feedthrough noise. The existing method of modeling the Vccin feedthrough noise is based on circuit simulation. Circuit models are highly complex as different components such as the FIVR power bridges, bridge drivers, MIM capacitors, package inductors, package power planes, and the Vccin network need to be modeled. Convergence issues are very frequent in full chip circuit simulations and it typically takes many iterations. Hence design optimization is difficult to carry out using circuit simulations. In this article, a state-space-based time-domain method is proposed to model the Vccin feedthrough noise based on G-parameters and S-parameters of the FIVR and the Vccin network. The state-space models are generated using the vector-fitting algorithm. The proposed method simplifies the construction of the Vccin feedthrough models and improves the convergence time.