Abstract
Intel® introduced an energy efficient SoC power delivery scheme utilizing fully-integrated high-frequency voltage regulators along the roadmap of Moore's law scaling. From 22nm process to 14nm or even 10nm, circuit blocks shrink and the embedded passives are scaled sequentially in the similar manner. A major challenge in the on-die VR design is to achieve sufficient integration and minimization of the required components, while still maintaining high power efficiency and multi-phase switching capability. This allows SoC to continue delivering a compelling power performance benefit to support the scaling process. In this paper, the optimized performance metrics of the silicon integrations are presented with measured implications and correlated simulations. The new generation microprocessor is demonstrated to be powered by a highly configurable VR solution of wide voltage and frequency range that facilitates potentially 50% more energy saving and peak available power increase.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
More From: 2017 China Semiconductor Technology International Conference (CSTIC)
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.