NoC based Efficient RTL Design and Verification of SoCWire BUS Protocol

Abstract

System on Chip Wire (SoCWire) is a Network on Chip (NoC) based design that composed of intellectual property blocks (IP) and interconnects based on space wire standard, was successfully implemented in Venus Express Monitoring Camera (VMC) mission and proposed to implement in Solar Orbital mission in future. The efficient and accurate implementation of SoCWire is the main concern in this work. A solution for single bit error detection and correction with hamming code for 8 bit data has been proposed, so that the accuracy of the design is improved with cost of extra resources and we can save nearly 19.2 μs time that is required to link re-initialization also the speed of the design is improved compared to conventional Codec. For routing data of many codec from one node to many other nodes SoCWire Switch is implement with crossbar based switch for 8 ports and achieved maximum frequency 179.743 MHz and 5% device utilization can be saved compared to [1]. These functionality and design performance are achieved with coding level change in VHDL for SoCWire. The design is synthesized on Xilinx ISE 12.1. The Target FPGA is XCVLX-60 which belongs to Xilinx Virtex 4 QPro.