Intel Cyclone Research Articles

Optimal concurrency on FPGA for lightweight medical image encryption

Digitized forms of images do widely used for medical diagnostics. To maintain the privacy of an individual in e-health care applications, securing the medical image becomes essential. Hence exclusive encryption algorithms have been developed to protect the confidentiality of medical images. As an alternative to software implementations, the realization of image encryption architectures on hardware platforms such as FPGA offers significant benefit with its reconfigurable feature. This paper presents a lightweight image encryption scheme for medical image security feasible to realize as concurrent architectural blocks on reconfigurable hardware like FPGA to achieve higher throughput. In the proposed encryption scheme, Lorentz attractor’s chaotic keys perform the diffusion process. Simultaneously, the pseudo-random memory addresses obtained from a Linear Feedback Shift Register (LFSR) circuit accomplishes the confusion process. The proposed algorithm implemented on Intel Cyclone IV FPGA (EP4CE115F29C7) analyzed the optimal number of concurrent blocks to achieve a tradeoff among throughput and resource utilization. Security analyses such as information entropy, histogram, correlation, and PSNR confirms the algorithm’s encryption quality. The strength of diffusion keys was ensured by randomness verification through the standard test suite from the National Institute of Standards and Technology (NIST). The proposed scheme has a larger keyspace of 2384 that guarantees good confusion through near-zero correlation, and successful diffusion with a PSNR of <5 dB towards the statistical attacks. Based on the hardware analysis, the optimal number of concurrent architectural blocks (2 N) on the chosen FPGA to achieve higher throughput (639.37 Mbps), low power dissipation (138.85 mW), minimal resource utilization (1268 Logic Elements) and better encryption quality for the proposed algorithm is recommended as 4 (with N = 2).

Low Power QC-LDPC Decoder Based on Token Ring Architecture

The article presents an implementation of a low power Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder in a Field Programmable Gate Array (FPGA) device. The proposed solution is oriented to a reduction in dynamic energy consumption. The key research concepts present an effective technology mapping of a QC-LDPC decoder to an LUT-based FPGA with many limitations. The proposed decoder architecture uses a distributed control system and a Token Ring processing scheme. This idea helps limit the clock skew problem and is oriented to clock gating, a well-established concept for power optimization. Then the clock gating of the decoder building blocks allows for a significant reduction in energy consumption without deterioration in other parameters of the decoder, particularly its error correction performance. We also provide experimental results for decoder implementations with different QC-LDPC codes, indicating important characteristics of the code parity check matrix, for which an energy-saving QC-LDPC decoder with the proposed architecture can be designed. The experiments are based on implementations in the Intel Cyclone V FPGA device. Finally, the presented architecture is compared with the other solutions from the literature.

Design and investigation of low-complexity Anurupyena Vedic multiplier for machine learning applications

The current world of computers is based on machine leaning and profound learning towards artificial intelligence. In recent investigations, parallelisms are used to solve difficult problems. For the implementation of the FPGA, new architectures have been built using design techniques VLSI and parallel computing technologies. Research on reconfigurable computing, machine learning and signal processing should be constantly monitored in the development of artificial intelligence. Energy-restricted computer devices should be continuously developed to support algorithms in the machine learning process. In machine learning algorithms, multipliers and adders play a significant role. In ALU, Convolutionary Neural Network (CNN) and Deep Neural Networks (DNN), the multiplier is an energy-consuming factor of signal processing. In this project, for the DNN, the high-speed Vedic multiplier has been introduced. The versions of the parallel–parallel (PP), serial–parallel (SP) and two-speed (TS) multipliers are compared to the standard 64-, 32- and 16-bit models. The results are obtained for an Intel Cyclone V 5CSEMA5U23C6 FPGA, using the Intel Quartus 17.0 software suite.

FPGA-Based Low-Visibility Enhancement Accelerator for Video Sequence by Adaptive Histogram Equalization With Dynamic Clip-Threshold

In the natural and practical scenario, the captured video sequence under bad weather situations or low light conditions often suffers from poor visibility and low-contrast problems. This hurts the performance of the high-level processing, e.g. object tracking or recognition. In this paper, we develop an FPGA-based low-visibility enhancement accelerator for video sequence by adaptive histogram equalization with dynamic clip-threshold (AHEwDC) which is determined by the visibility assessment. The main goal is to improve the low visibility with high image quality for both hazy and low-light video sequences in real-time. Firstly, a concept to quantify the visual perception based on supervised learning is to estimate the visibility score. Then, to avoid the problem of noise amplification in the conventional method, we propose a visibility assessment model to find an optimal clip-threshold. The contrast energy of gray channel, yellow-blue channel and red-green channel, average saturation, and gradients are statistical features in the model to describe the visibility of an image. Finally, to meet the speed requirement for video sequence processing, a specified hardware architecture for both visibility assessment and AHEwDC is implemented on FPGA. Besides, a mean spatial filter for cumulative distribution functions (CDFs) of the AHE is developed for suppressing the noise caused by a single-color local region. The demonstration system on the DE1-SoC platform with the Intel Cyclone V FPGA device with the max working frequency of 75.84 MHz is capable of processing 30 fps FHD ( $1920\times 1080$ ) video.

FPGA Design of Elliptic Curve Cryptosystem (ECC) for Isomorphic Transformation and EC ElGamal Encryption

Attacking or tampering with sensitive data continues to increase risks to economic processes or human activities. These risks are significant key factors to improve the development and implementation of security systems. Therefore, improving cryptography is essentially needed to enhance the security of critical data. For example, elliptic curve cryptography (ECC) over the Galois field GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">163</sup> ) is one of the public-key (asymmetric) cryptographic techniques, in which demands mapping a message (163-bit) to a point in the prime subgroup of the elliptic curve. To the best of our knowledge, mapping methods are not yet available on Field-Programmable Gate Arrays (FPGAs). Also, asymmetric encryption schemes often do not consider encrypting/decrypting data packets because of their computation complexity and performance limitations. In this letter, we propose and develop a concurrent reconfigurable cryptosystem to encrypt and decrypt stream of data using ECC on FPGA. First, we present hardware design and implementation to map a plain message on the elliptic curve based on isomorphic transformation, then second, we architect the elliptic curve ElGamal public-key encryption method by using point addition and multiplication on Koblitz elliptic curve on FPGA. Our proposed cryptosystem is synthesized and implemented on Intel Cyclone 10 GX and Xilinx Kintex-7 FPGAs to evaluate throughput, and it achieves 25.73-57.1 Mbps.

FPGA-Oriented LDPC Decoder for Cyber-Physical Systems

A potentially useful Cyber-Physical Systems element is a modern forward error correction (FEC) coding system, utilizing a code selected from the broad class of Low-Density Parity-Check (LDPC) codes. In this paper, development of a hardware implementation in an FPGAs of the decoder for Quasi-Cyclic (QC-LDPC) subclass of codes is presented. The decoder can be configured to support the typical decoding algorithms: Min-Sum or Normalized Min-Sum (NMS). A novel method of normalization in the NMS algorithm is proposed, one that utilizes combinational logic instead of arithmetic units. A comparison of decoders with different bit-lengths of data (beliefs that are messages propagated between computing units) is also provided. The presented decoder has been implemented with a distributed control system. Experimental studies were conducted using the Intel Cyclone V FPGA module, which is a part of the developed testing environment for LDPC coding systems.

Hardware Evolution Based on Improved Simulated Annealing Algorithm in Cyclone V FPSoCs

Evolvable hardware (EHW) is an emerging area of research that uses evolutionary algorithms (EAs) to construct circuits without manual intervention. However, this technique confronts two major issues: the evolution efficiency of structures and the computational efficiency of EAs. To address these issues, we construct a novel virtual reconfigurable circuit (VRC) based on artificial neural network (ANN) architecture and develop a promising EA based on improved simulated annealing (ISA) for the research of EHW. Here, ISA escapes the local optimization through an inner loop and expands new search space through an outer loop. Furthermore, several strategies are proposed for the representation, perturbation and selection of solutions (individuals) to reduce the computational burden throughout the entire evolution process. The use of an Intel Cyclone V field programmable system-on-chip (FPSoC) further accelerates the execution of the algorithm and provides designers with much more high-level processing power than that provided by soft-cores. The obtained results show that the proposed method achieves high-speed processing and improves computational efficiency. The results also show that the method has good flexibility and scalability.

Fixed point multi-bit approximate adder based convolutional neural network accelerator for digit classification inference

Approximate computing is a rapidly growing technique to speed up applications with less computational effort while maintaining the accuracy of error-resilient applications such as machine learning and deep learning. Inheritance properties of the machine and deep learning process give freedom for the designer to simplify the circuitry to speed up the computation process at the expense of accuracy of computational results. Fundamental blocks of any computation are adders. In order to optimize it for better performance, 2-bit multi-bit approximate adders (MAPX) are proposed in this work which breaks the lengthy carry chain. In contrast with other approximate larger width adders, instead of using accurate adders for the most significant part, here proposed 2-bit MAPX-1 and MAPX-2 adders are arranged in various ways to compose most and least significant parts. Designed 8-bit and 16-bit adders are evaluated for their performance and error characteristics. Proposed 2-bit MAPX-2 shows better error characteristics whose MED is 0.250 while occupying less area and MAPX-1 consumes less power and delay at the cost of accuracy. Among the extended adders, MAPX 8-bit adder design1 outperforms the best performing APX based 8-bit adder design1. The error performance of it is improved by 14%, 42.1% and 50.4% compared to the existing well-performing APX 8-bit Design1, Design2 and Design3 respectively. Similarly, proposed MAPX 16-bit Design1 exhibits overwhelming performance compared to best performing APX 16-bit Design1, and its error performance is improved by 24.3%, 34.9% and 50.3% compared to APX 16-bit Design1, Design2 and Design3 respectively. In order to evaluate the proposed adder for a real application, extended MAPX 16-bit Design1 is fit in the convolution layer of Low Weights Digit Detector (LWDD) convolutional neural network-based digit classification system. Our modified system accelerates the computation process by 1.25 factors while exhibiting the accuracy of 91% and it best fits error-tolerant real applications. All the adders are synthesized and implemented in the Intel Cyclone IV EP4CE22F17C6N FPGA.

Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation

Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system. The proposed adder uses more circuit area than the conventional SD adders when those adders are realized on ASIC. However, the proposed adder uses 20% less number of logic elements than the conventional SD adder when those adders are realized on a field-programmable gate array (FPGA) which is made up of 4-input 1-output LUT such as Intel Cyclone IV FPGA.

A Two-Speed, Radix-4, Serial–Parallel Multiplier

In this paper, we present a two-speed, radix-4, serial-parallel multiplier for accelerating applications such as digital filters, artificial neural networks, and other machine learning algorithms. Our multiplier is a variant of the serial–parallel (SP) modified radix-4 Booth multiplier that adds only the nonzero Booth encodings and skips over the zero operations, making the latency dependent on the multiplier value. Two subcircuits with different critical paths are utilized so that throughput and latency are improved for a subset of multiplier values. The multiplier is evaluated on an Intel Cyclone V field-programmable gate array against standard parallel–parallel and SP multipliers across four different process–voltage–temperature corners. We show that for bit widths of 32 and 64, our optimizations can result in a $1.42\times $ – $3.36\times $ improvement over the standard parallel Booth multiplier in terms of area–time depending on the input set.

Loop Unrolling for Energy Efficiency in Low-Cost Field-Programmable Gate Arrays

Field-programmable gate arrays (FPGAs) are used for a wide variety of computations in low-cost embedded systems. Although these systems often have modest performance constraints, their energy consumption must typically be limited. Many FPGA applications employ repetitive loops that cannot be straightforwardly split into parallel computations. Performing a loop sequentially generally requires high-speed clocks that consume considerable clock power and sometimes require clock generation using a phase-locked loop (PLL). Loop unrolling addresses the high-speed clock issue, but its use often leads to significant combinational glitch power. In this work, a computer-aided design (CAD) approach that unrolls loops for designs targeted to low-cost FPGAs is described. Our approach considers latency constraints in an effort to minimize energy consumption for loop-based computation. To reduce glitch power, a glitch-filtering approach is introduced that provides a balance between glitch reduction and design performance. Glitch-filter enable signals are generated and routed to the filters using resources best suited to the target FPGA. Our approach automatically inserts glitch filters and associated control logic into a design prior to processing with FPGA synthesis, place, and route tools. Our energy-saving loop-unrolling approach has been evaluated using five benchmarks often used in low-cost FPGAs. The energy-saving capabilities of the approach have been evaluated for an Intel Cyclone IV and a Xilinx Artix-7 FPGA using board-level power measurement. The use of unrolling and glitch filtering is shown to reduce energy by at least 65% for an Artix-7 device and 50% for a Cyclone IV device while meeting design latency constraints.

Frequency-Domain Power Delivery Network Self-Characterization in FPGAs for Improved System Reliability

Modern field-programmable gate arrays (FPGAs) operate at a core voltage around 1 V and therefore even small voltage fluctuations lead to timing violations and logic errors. The power delivery network (PDN) between the voltage regulator and the FPGA core must be carefully designed to achieve a low output impedance over a broad range of frequencies. Simulation tools are commonly used to estimate the impedance, however, they do not account for aging, component variations, and inaccurate modeling of parasitic elements, all of which lead to PDN design deviation. In this paper, two schemes are presented: first, to extract the dc resistance in the power delivery path, and second, to identify the high impedance frequency band(s) in the PDN. The embedded impedance extraction tool is synthesized within the FPGA load, in coordination with a mixed-signal current-mode dc–dc converter. A new self-calibrated carry-chain-based analog-to-digital converter (CC-ADC) is used for high-speed sampling of the core voltage. The proposed schemes are demonstrated on an Intel Cyclone IV FPGA board. Real-time IR -drop compensation is shown to eliminate logic errors in an finite impulse response filter application. It is also shown that the fail/pass map of a crossbar application matches well with the extracted impedance profile versus voltage and frequency. By modifying the PDN based on the extracted results, the voltage operating range and reliability of the crossbar application are greatly extended.

Robust Self-Calibrated Dynamic Voltage Scaling in FPGAs With Thermal and IR-Drop Compensation

Field programmable gate arrays (FPGAs) are widely used in telecom, medical, military, cloud computing, and other high-performance computing applications, thanks to their unique combination of parallel hardware execution and reprogrammability. During compilation, the computer-aided design (CAD) tool estimates the maximum operating frequency of the user application based on the worst case timing analysis of the critical path at a fixed nominal supply voltage, which usually results in significant voltage or frequency margin. Hence dynamic voltage scaling (DVS) has great potential to reduce the power overhead in FPGAs; however, the reprogrammability of FPGAs make a safe implementation of DVS for any application that could be programmed into the FPGA challenging. This work presents a robust universal DVS scheme for FPGAs intended to run on a system production line, or regularly during each FPGA power-up. The proposed scheme requires the FPGA to be programmed twice: offline self-calibration and online DVS. During the offline self-calibration, the FPGA frequency and core voltage operating limits at different self-imposed temperatures are automatically found and stored in a calibration table (CT). During online operation, the power stage refers to the CT and dynamically adjusts the core voltage according to the FPGA temperature and the resistive voltage drop in the power delivery path. The proposed DVS scheme is demonstrated on a 60-nm Intel Cyclone IV FPGA, with a digitally controlled dc–dc converter, leading to 40% power savings in two typical applications.

ES-TRNG: A High-throughput, Low-area True Random Number Generator based on Edge Sampling

In this paper we present a novel true random number generator based on high-precision edge sampling. We use two novel techniques to increase the throughput and reduce the area of the proposed randomness source: variable-precision phase encoding and repetitive sampling. The first technique consists of encoding the oscillator phase with high precision in the regions around the signal edges and with low precision everywhere else. This technique results in a compact implementation at the expense of reduced entropy in some samples. The second technique consists of repeating the sampling at high frequency until the phase region encoded with high precision is captured. This technique ensures that only the high-entropy bits are sent to the output. The combination of the two proposed techniques results in a secure TRNG, which suits both ASIC and FPGA implementations. The core part of the proposed generator is implemented with 10 look-up tables (LUTs) and 5 flip-flops (FFs) of a Xilinx Spartan-6 FPGA, and achieves a throughput of 1.15 Mbps with 0.997 bits of Shannon entropy. On Intel Cyclone V FPGAs, this implementation uses 10 LUTs and 6 FFs, and achieves a throughput of 1.07 Mbps. This TRNG design is supported by a stochastic model and a formal security evaluation.

Implementation of Multiple-Input Multiple-Output Dynamic Matrix Control Algorithm for Fast Processes Using Field Programmable Gate Array

The objective of this paper is to describe an implementation of a Dynamic Matrix Control (DMC) algorithm for a Field Programmable Gate Array (FPGA). The DMC algorithm is implemented in a universal version for multiple-input multiple-output dynamic processes. The results of real experiments are presented in which the DE2i-150 development board produced by Terasic with Intel Cyclone IV GX chip is used. As the controlled process a laboratory stand especially developed for this work is used, which is a dynamic system with two manipulated inputs and two controlled outputs. The implemented DMC controller is very fast, it may be used for controlling processed which need sampling periods of a millisecond order.

Design and Development of Embedded Turbine Supervisory Instruments Based on ARM and Linux

Aiming at issues of the modern embedded turbine supervisory instruments such as simplistic function, weak process power, low efficiency and so on, the technique of double CPUs with the cores of Intel PXA270 and Cyclone II EP2C20 microprocessors is employed in the present design. With embedded linux operating system and the developing platform of Qt software implemented, important functions such as data acquisition, data transfer based on TCP/IP protocols, display of data waveform, local storage of data, data analysis, elementary fault diagnosis and so forth can be achieved all together in a single facility. After tested on the Rotor Kit 4 of Bently Nevada and applied on 300MW turbine of the Power System Dynamic Simulation Laboratory in North China Electric Power University, the newly designed embedded turbine supervisory instruments show that the technique of double CPUs is effective, and the portable system can overcome the deficiencies of the modern embedded turbine supervisory instruments as mentioned above.