Design and investigation of low-complexity Anurupyena Vedic multiplier for machine learning applications

Abstract

The current world of computers is based on machine leaning and profound learning towards artificial intelligence. In recent investigations, parallelisms are used to solve difficult problems. For the implementation of the FPGA, new architectures have been built using design techniques VLSI and parallel computing technologies. Research on reconfigurable computing, machine learning and signal processing should be constantly monitored in the development of artificial intelligence. Energy-restricted computer devices should be continuously developed to support algorithms in the machine learning process. In machine learning algorithms, multipliers and adders play a significant role. In ALU, Convolutionary Neural Network (CNN) and Deep Neural Networks (DNN), the multiplier is an energy-consuming factor of signal processing. In this project, for the DNN, the high-speed Vedic multiplier has been introduced. The versions of the parallel–parallel (PP), serial–parallel (SP) and two-speed (TS) multipliers are compared to the standard 64-, 32- and 16-bit models. The results are obtained for an Intel Cyclone V 5CSEMA5U23C6 FPGA, using the Intel Quartus 17.0 software suite.