Insulator Metal Oxide Semiconductor Research Articles

Evaluation of the Coulomb-limited mobility in high-κ dielectric metal oxide semiconductor field effect transistors

An efficient numerical method for the evaluation of the Green’s function used in the calculation of the Coulomb-limited electron mobility in high-κ metal oxide semiconductor field effect transistors is presented. This simple method is applicable to gate stacks with an arbitrary number of layers of varying dielectric permittivity. A charge profile with varying dielectric profile is demonstrated to show an increase in Coulomb-limited mobility of 16% in comparison to a point charge located at the interface. A metal gate reduces the scattering potential due to its infinite dielectric constant which leads to lesser impact of charge in comparison to a polysilicon gate. The Coulomb-limited mobility for devices having identical equivalent oxide thickness of 0.5–0.8 nm with (a) a hafnium silicate interfacial layer (IL) and (b) zero IL is presented.

Detailed simulation study of embedded SiGe and Si:C source/drain stressors in nanoscaled silicon on insulator metal oxide semiconductor field effect transistors

Strained silicon techniques have become an indispensable technology feature, enabling the momentum of semiconductor scaling. Embedded silicon-germanium (eSiGe) is already widely adopted in the industry and delivers outstanding p-metal oxide semiconductor field effect transistor (MOSFET) performance improvements. The counterpart for n-MOSFET is embedded silicon-carbon (eSi:C). However, n-MOSFET performance improvement is much more difficult to achieve with eSi:C due to the challenging process integration. In this study, detailed TCAD simulations are employed to compare the efficiency of eSiGe and eSi:C stressors and to estimate their potential for performance enhancements in future nanoscaled devices with gate lengths down to 20nm. It is found that eSiGe as a stressor is superior to eSi:C in deeply scaled and highly strained devices due to its easier process integration, reduced parasitic resistance, and nonlinear effects in the silicon band structure, favoring hole mobility enhancement at high strain levels.

Simulation of asymmetric doped high performance silicon on insulator metal oxide semiconductor field effect transistors for very large scale integrated complementary metal oxide semiconductor technologies

Asymmetric halo and extension implantations are examined by simulation for their usability in 45 and 32 nm technology high performance silicon on insulator metal oxide semiconductor field effect transistors (SOI-MOSFETs). Tilted halo and extension implantations from the source side show higher saturation currents and lower drain overlap and junction capacitances, which improve the intrinsic MOSFET power delay product. Furthermore the asymmetric doping profile leads to an inverter chain speed benefit. The stronger short channel effect, present in these devices, can be reduced by a low dose drain side halo implantation simultaneously maintaining a transistor performance improvement from asymmetric doping. This optimized transistor design is successfully transferred from the 45 into the 32 nm technology.

Scaling potential and MOSFET integration of thermally stable Gd silicate dielectrics

We investigate the potential of gadolinium silicate (GdSiO) as a thermally stable high- k gate dielectric in a gate first integration scheme. There silicon diffuses into gadolinium oxide (Gd 2O 3) from a silicon oxide (SiO 2) interlayer specifically prepared for this purpose. We report on the scaling potential based on detailed material analysis. Gate leakage current densities and EOT values are compatible with an ITRS requirement for low stand by power (LSTP). The applicability of this GdSiO process is demonstrated by fully functional silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs).

Effects of Ion Implantation Damage on Elevated Source/Drain Formation for Ultrathin Body Silicon on Insulator Metal Oxide Semiconductor Field-Effect Transistor

For high-speed and low-power performance, ultrathin body (UTB) silicon on insulator (SOI) metal oxide semiconductor field-effect semiconductors (MOSFETs) with an elevated source/drain (ESD) have been investigated using selectively epitaxial growth (SEG) technology. In this work, we found that the morphology of a SEG layer on an ultrathin Si film and the crystallinity of the top Si film are strongly dependent on ion implantation damage. The morphology and surface roughness of SEG layers were investigated by field emission scanning electron microscopy (FE-SEM) and the crystallinities of the top silicon films with and without ion implantation were characterized by atomic force microscopy (AFM) and Rutherford backscattering spectroscopy (RBS), respectively. Furthermore, to suppress ion implantation damage, a SEG layer was formed before ion implantation for source drain extension (SDE) formation by the sacrificial sidewall spacer method. As results, UTB SOI-MOSFETs with a flat ESD were successfully fabricated by the proposed method.

Characteristics of Silicon-on-Low k Insulator Metal Oxide Semiconductor Field Effect Transistor with Metal Back Gate

We proposed a silicon-on-low k insulator (SOLK) metal oxide semiconductor field effect transistor (MOSFET) with a metal back gate for high-speed and ultralow power devices. In this work, Benzocyclobutene (BCB) and tetramethyl ammonium hydroxide (TMAH) were employed to fabricate SOLK Devices without damaging the transistor channels. We successfully fabricated the proposed submicron fully depleted (FD) SOLK MOSFETs with a metal back gate. The process technologies and electrical properties of SOLK MOSFETs were introduced in detail. Furthermore, threshold voltage shift was obtained at 55 mV/V using a NMOSFET and at 35 mV/V using a PMOSFET and drain current characteristics are enhanced by the back gate bias.

Scalable gate first process for silicon on insulator metal oxide semiconductor field effect transistors with epitaxial high-k dielectrics

A “gate first” silicon on insulator (SOI) complementary metal oxide semiconductor process technology for direct evaluation of epitaxial gate dielectrics is described, where the gate stack is fabricated prior to any lithography or etching step. This sequence provides perfect silicon surfaces required for epitaxial growth. The inverted process flow with silicon dioxide (SiO2)/polysilicon gate stacks is demonstrated for gate lengths from 10μm down to 40nm on a fully depleted 25nm thin SOI film. The interface qualities at the front and back gates are investigated and compared to conventionally processed SOI devices. Furthermore, the subthreshold behavior is studied and the scalability of the gate first approach is proven by fully functional sub-100nm transistors. Finally, a fully functional gate first metal oxide semiconductor field effect transistor with the epitaxialhigh-k gate dielectric gadolinium oxide (Gd2O3) and titanium nitride (TiN) gate electrode is presented.

Modeling Silicon on Insulator MOS Transistors with Nonrectangular-Gate Layouts

This work presents a new and simple approach for modeling silicon on insulator metal-oxide-semiconductor (MOS) dc characteristics for nonrectangular layout devices, based on decomposition of the original shape into trapezoidal parts and on an accurate but simple model of the trapezoidal layout transistor. Analytical expressions relating geometrical parameters and terminal current and voltages are presented for several shapes, such as L, U, T, and S, and other well-known devices such as the edgeless transistor and the asymmetric trapezoidal gate transistor. The proposed closed-form analytical expressions show good agreement with measured data and three-dimensional simulation results.

Compact Modeling of Weak Inversion Generation Transients in SOI MOSFETs

Generation-type drain current transients in advanced (down to 50 nm gate length) floating-body, partially depleted silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs) are investigated by 2D numerical simulation in weak inversion operation. An original compact analytical model is derived for the pure transient weak inversion operation and validated on both elementary and realistic 2D structures. The proposed subthreshold transient compact model allows accurate prediction of the influence of the generation lifetime, surface velocity (or interface state density), oxide thickness, and substrate doping on the floating-body-related transient behavior and duration, which is essential for advanced transistor optimization and subsequent circuit applications. Moreover, our model is a unique, robust tool for the electrical characterization of submicrometer SOI transistors because it allows the carrier lifetime extraction independently of the channel carrier mobility and device effective gate length. Finally, the model is successfully used in high-temperature operation for drain current transient prediction and generation lifetime extraction. © 2004 The Electrochemical Society. All rights reserved.

Novel Silicon On Insulator Metal Oxide Semiconductor Field Effect Transistors with Buried Back Gate

One of the most promising ways of realizing metal oxide semiconductor field effect transistors (MOSFETs) with high speed and ultralow power consumption is by varying the threshold voltage of fully depleted silicon on insulator (FD-SOI) MOSFETs by changing back gate bias. We have studied FD-SOI MOSFETs with buried back gate by experiment and simulation in order to realize both high-performance and low-voltage ULSIs. It was confirmed that the back gate is very effective not only for increasing the ON current in the active mode but also for decreasing the cut-off current in the standby mode by controlling the threshold voltage.

Deep-submicron drain current to radio frequency silicon on insulator metal oxide semiconductor field-effect transistor macromodel for designing microwave circuits

A submicron radio frequency (RF) fully depleted silicon on insulator (SOI) metal oxide semiconductor field-effect transistor (MOSFET) macromodel based on a complete extrinsic small-signal equivalent circuit and an improved computer-aided design model for the intrinsic device is presented. Because the intrinsic device model is charge based, our RF SOI MOSFET model can be used in both small- and large-signal analyses. The present analytical model is used for successfully designing microwave oscillators at 5.8 and 12 GHz in deep-submicron SOI complementary metal oxide semiconductor technology. © 2002 Wiley Periodicals, Inc. Int J RF and Microwave CAE 12, 428–438, 2002. Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mmce10045

Numerical simulation of quantum effects in high-k gate dielectric MOS structures using quantum mechanical models

In this paper the electrical characteristics of metal oxide semiconductor (MOS) capacitors with high-k gate dielectric are investigated with quantum mechanical models. Both the self-consistent Schrodinger–Poisson (SP) model and the density gradient (DG) model are solved simultaneously to study quantum confinement effects (QCEs) for MOS capacitors. A computationally efficient parallel eigenvalue solution algorithm and a robust monotone iterative (MI) finite volume (FV) scheme for the SP and DG models are systematically proposed and successfully implemented on a Linux cluster, respectively. With the developed simulator, we can extract the effective gate oxide thickness from capacitance voltage (C-V) measurements for TaN and Al gate NMOS capacitors with Zr O2 and Si O2 gate dielectric materials. We found that quantization effects of 5.0 nm Zr O2 MOS samples cannot be directly equivalent to commonly quoted effects of 1.5 nm Si O2 MOS samples. Achieved benchmarks are also included to demonstrate excellent performances of the proposed computational techniques.  2002 Elsevier Science B.V. All rights reserved.

Formation of SiGe on Insulator Structure and Approach to Obtain Highly Strained Si Layer for MOSFETs

The formation of a SiGe layer on insulators, which can be realized by applying the separation by implanted oxygen (SIMOX) technique to SiGe layers, is essential for fabricating strained silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs). In this study, the SIMOX process for SiGe films is examined in terms of Ge diffusion during SIMOX annealing and the annealing temperature. It is found that the SIMOX annealing at temperature above 1300°C is necessary to realize uniform buried oxides, even though the melting point of SiGe crystal decreases with the Ge content. Ge diffusion during high-temperature annealing must also be taken into account when preparing the SiGe layer for SIMOX. These facts indicate that the realization of a SiGe layer on buried oxides is difficult with the simple SIMOX process for SiGe crystal, particularly so in the case of high Ge content. In order to overcome this problem, the double layer SiGe structure on an insulator is proposed and the effectiveness of this structure on the increase of strain in Si is verified experimentally. The strain relaxation of the SiGe layer with higher Ge content, which is grown on the SiGe layer with lower Ge content, is observed with expanding of the under-layer.

Thickness measurements for ultrathin-film insulator metal–oxide–semiconductor structures using Fowler–Nordheim tunneling current oscillations

An interference method is introduced to analyze tunneling current oscillations, and a fresh way to extrapolate the oxide thickness in ultrathin-film insulator metal–oxide–semiconductor structures by using the oscillations in the Fowler–Nordheim tunneling currents is presented. A comparison between this extrapolation algorithm and a previous algorithm using tunneling current oscillations shows that the new extrapolation algorithm provides a more accurate and convenient solution to a first principles calculation especially for ultrathin oxide. Another important feature of the proposed method is that it can be applied to various shapes of potential barriers and wells.

Analyses of the Radiation-Caused Characteristics Change in SOI MOSFETs Using Field Shield Isolation

Reliability against radiation is an important issue in silicon on insulator metal oxide semiconductor field effect transistors (SOI MOSFETs) used in satellites and nuclear power plants and so forth which are severely exposed to radiation. Radiation-caused characteristic change related to the isolation-edge in an irradiated environment was analyzed on SOI MOSFETs. Moreover short channel effects for an irradiated environment were investigated by simulations. It was revealed that the leakage current which was observed in local oxidation of silicon (LOCOS) isolated SOI MOSFETs was successfully suppressed by using field shield isolation. Simulated potential indicated that the potential rise at the LOCOS edge can not be seen in the case of field shield isolation edge which does not have physical isolation. Also it was found that the threshold voltage shift caused by radiation in short channel regime is severer than that in long channel regime. In transistors with a channel length of 0.18 µm, a potential rise of the body region by radiation-induced trapped holes can be seen in comparison with that of 1.0 µm. As a result, we must consider these effects for designing deep submicron devices used in an irradiated environment.

Buried-gate oxide thinning during epitaxial lateral overgrowth for dual-gated metal–oxide–semiconductor field-effect transistors

During epitaxial lateral overgrowth of single‐crystal silicon over thermal SiO2, in the low‐pressure chemical vapor deposition reactor environment, thinning and even pinholes can occur in the underlying gate oxide of in dual‐gated silicon on insulator metal–oxide–semiconductor field‐effect transistors (MOSFETs). The epitaxial lateral overgrowth was grown using dichlorosilane (DCS), HCl, and H2 at 970 °C and 40 Torr. Although the etch rate was very small, the thinning was large enough to change the bottom channel threshold voltage (Vt). Oxide thickness measurements, obtained by ellipsometry and by profilometer measurements, indicated an etch rate of about 0.1 nm/min, which was independently confirmed from MOSFET Vt shift measurements. The oxide etch rate decreased with increasing concentration of HCl and was less for oxides grown from heavily arsenic‐doped than from lightly doped boron silicon.

An Investigation on the Short Channel Effect for 0.1 µm Fully Depleted SOIMOSFET Using Equivalent One Dimensional Model

An analytical model for the short channel effect for the silicon on insulator metal oxide semiconductor field effect transistor (SOIMOSFET) is proposed. The two dimensional potential problem is reduced to a one dimensional problem, using a virtual electrode which is equivalent to the drain and the source electrodes. The behavior for the short channel effect is also discussed using this model.

Current-Voltage Characteristics of Silicon on Insulator Metal Oxide Semiconductor Field Effect Transistors in Ballistic Mode

Current-voltage characteristics of ultrathin silicon on insulator n-type MOSFETs (metal oxide semiconductor field effect transistors) operating in ballistic transport mode are given. They are derived with the similar guiding principle as that used in quantum point contact. The obtained result is independent of channel length, and is expressed with elementary parameters without depending on ambiguous carrier mobility. They show triode and pentode operational modes similarly to the normal MOSFET. When inversion carriers are degenerate, saturation current is independent of temperature and is proportional to the carrier density to the power of 1.5.