Input Transistor Research Articles

Analysis of nonlinear effects and calculation of EMC characteristics of SHF amplifier based on heterojunction bipolar transistor

Analysis of nonlinear properties of amplifier, based on heterojunction bipolar transistor, under the influence of intensive interferences at the amplifier input was carried out with Walter’s series method. It is shown that nonlinearity level and character depend on mutual compensation of harmonics, which are generated into base and collector circuits, and it is also dependent on correlation between Taylor expansion coefficients of nonlinear elements of equivalent circuit near operating point and transistor input impedance.

A [formula omitted] CMOS bandgap reference featuring a 1.5–6 mA output driving current and a Miller-effect startup circuit

We present a pure CMOS bandgap voltage reference with a low quiescent current and high output current driving capability. The circuit sources a driving current of up to 1.5mA with the reference voltage kept above 98.5% of its designated 1.2V, and up to 6mA before the voltage drops to 90%. The circuit achieves a very low supply current of 13μA, a low power of 30μW, a line regulation of ±2.5mV/V and a load regulation of ±7mV/mA. The reference is implemented in a 1μm pure CMOS process with Vtn≈|Vtp|≈0.7V at 25∘C using substrate pnp. A startup circuit, which shuts down itself after a controlled delay using Miller effect, is also introduced. By utilizing the body effect of the input transistors, the turn-on threshold of the startup circuit is raised to about 1V, making it a perfect match for the reference architecture. Silicon measurements are in good agreement with simulations.

Gate dielectric degradation in CMOS inverters

To study the gate oxide degradation under stress conditions closer to the actual operation of devices in circuits, in this work, CMOS inverters have been stressed using DC and pulsed signals at the input. Uniform and non-uniform Fowler-Nordheim and Channel Hot Carrier stresses have been identified as those governing the oxide degradation, depending on the input signal, and modifying the electrical response of the device. In particular, a decrease of the saturation current is observed, which depends on the transistor type (NMOS or PMOS), input signal, and stress time. The results show larger degradations in the NMOS when the input frequency is increased, which has been attributed to the Channel Hot Carriers contribution during the output state transitions in the inverter. Also the impact of the different stresses on the circuit output is analyzed and related to the degradation of the devices. A shift in the inverter voltage transfer characteristic has been observed, whose direction depends on the degradation that the transistors have suffered, being more important at elevated frequencies.

A Low-Power Reduced Kick-Back Comparator with Improved Calibration for High-Speed Flash ADCs

SUMMARY A novel low-power kick-back reduced comparator for usein high-speed flash analog-to-digital converters (ADC) is presented. Theproposed comparator combines cascode transistors to reduce the kick-backnoise with a built-in threshold voltage to remove the static power consump-tion of a reference. Without degrading other figures, the kick-back noiseis reduced by a factor 8, compared to a previous design without cascodetransistors. An improved calibration structure is also proposed to improvelinearity when used in an ADC. Simulated in a standard CMOS technologythe comparator consumes 106.5 μW at 1.8V power supply and 1GHz clockfrequency. key words: comparator, kick-back, calibration, low-power, flash ADC 1. Introduction Today’s high data rates necessitate the use of high-speedflash Analog-to-Digital Converters (ADC). The perfor-mance of these converters in terms of speed, power-consumption, and linearity greatly depends on the archi-tecture of the comparators used. Standard ADC designsconsist of an input-buffer/track and hold amplifier, a ref-erence ladder and a sense amplifier or S/R-type track andlatch comparator. In [1], a low power high-speed ADC de-sign was proposed, based on a switched type sense ampli-fier with built-in reference voltages. This omits the use ofa reference ladder and reduces the static power dissipation,yielding 10.6mW of power consumption at 1Gs/s and 4-bitresolution. A down-side of this design is that comparatorswitching generates considerable kick-back noise into theADC input, which necessitates the use of a low-impedancebuffer for driving the ADC, and so the overall power reduc-tion of this system is limited. Other comparators [2],[3]have been proposed with low kick-back noise. However,these approaches show a relatively high power consump-tion due to the need for a static reference ladder or due toa folded architecture. This paper presents a comparator us-ing the best of the two worlds: cascode transistors to reducethe kick-back noise while maintaining the low power con-sumption and removing the need of a static reference ladderdue to offsetting the input transistors.

Review and Analysis of the Radiation-Induced Degradation Observed for the Input Bias Current of Linear Integrated Circuits

It is shown that the variety of shapes of the input current versus dose curve observed in several ICs is due to circuit effects, depending on the architecture, the value of the currents and the bias conditions. When stages are cascaded, the degradation of the second stage may add or subtract current to the collector current of the input transistor. The variations of the collector currents can be evaluated using the variations of the supply current. It is then possible to model the compensation effects using basic equations and study the impact of irradiation conditions. In some cases, the effect of biasing the circuit during irradiation is to reduce the compensation mechanism leading to an stronger increase in the input current. When a peak shaped degradation curve is recorded, annealing may either induce an additional degradation or a recovery depending on which side of the peak irradiation has brought the circuit.

An SiC/GaN Detector/Front-End Detection System for High-Resolution Alpha-Particle Spectroscopy

An alpha-particle spectrometer has been assembled, consisting of an epitaxial 50 mum thick 4H silicon carbide (SiC) detector connected to a gallium-nitride (GaN) high-electron mobility transistor (HEMT) used as input transistor of the front-end electronics. The depleted layer of the SiC diode detector was sufficient to stop all alpha particles in the 4.8-MeV to 5.8-MeV energy range. An excellent energy resolution of ~ 0.9% has been obtained in this energy range at a temperature of 55degC. The energy-resolution limiting factor is found to be the dispersion of the energy loss in the gold Schottky contact, which acts as entrance window to the detector. We used a GaN front-end transistor because this material offers two important advantages over silicon: (1) it is a wide bandgap semiconductor and therefore is intrinsically more desirable for room and above-room temperature operation and (2) it can be grown on SiC substrates so as to realize SiC/GaN integrated systems. SiC-detector spectrometers are interesting in many nuclear applications where the operation environment is hostile, both in terms of ionising radiations and of high temperatures. Such applications include monitoring of ionising radiations in nuclear power plants and beam diagnostic in fundamental nuclear physics experiments.

Low Voltage Differential Input Stage With Improved CMRR and True Rail-to-Rail Common Mode Input Range

A scheme for low voltage rail-to-rail operation with improved common mode rejection ratio is introduced. It can operate with single supply voltages close to a transistor's threshold voltage and it is very compact and power efficient. It is based on a differential amplifier with floating gate input transistors featuring dynamical adjustment of a floating gate biasing voltage. This reduces significantly common mode voltage variations at the input terminals of the differential pair. The implementation of single ended two stage class AB operational amplifiers based on this scheme is discussed. Experimental results of a test chip in 0.5 mum CMOS technology that validates the proposed scheme are presented.

Broadband Active Balun Using Combined Cascode–Cascade Configuration

A new configuration is proposed for an active balun, which uses a cascode and cascade pair with the shared input transistor. It is designed in the IBM 8HP 130-nm BiCMOS process, which operates over a broad bandwidth up to 17 GHz where the imbalance of the differential output is less than 1.8 dB in amplitude and less then 10 in phase, over the input's dynamic range of -25-5 dBm, under the dc power consumption of 198.8 mW. The circuit contains no internal dc blocking capacitors so that the bandwidth's lower end frequency best extends as close to dc as possible. The circuit contains only one line inductor with the value of 0.2 nH, and the compacted layout is expected to fit in limited chip areas as small as 0.2 mm times 0.2 mm, which makes them well suited for built-in self-test applications, as well as general differential circuits requiring compact-sized broadband baluns.

An ultra low power CMOS pA/V transconductor and its application to wavelet filters

Two compact ultra low-power CMOS triode transconductor topologies denoted VLPT-gm and Delta-gm are proposed. In both circuits, input transistors are kept in the triode region to benefit from the lowest gm/ID ratio. This allows achieving a small-signal transconductance gm down to hundreds of pA/V, making such transconductors attractive for the synthesis of gm-C filters with cut-off frequencies in the range of Hz and sub-Hz. The gm value is adjusted by a well defined aspect-ratio (W/L) and drain-source voltage VDS, the latter a replica of the tuning voltage VTUNE imposed as drain-source voltage of input devices. VLPT-gm reaches a minimum gm of 1 nA/V, whereas Delta-gm exhibits a gm as low as 400 pA/V. Input-referred noise spectral density is typically 12.33 μV/Hz1/2 @ 1 Hz and 93.75 μV/Hz1/2 @ 1 Hz for VLPT-gm and Delta-gm, respectively. In addition, setting their gm equal to 1 nA/V and arranging them as first-order lossy integrators, Delta-gm presents higher bandwidth with respect to VLPT-gm. Cut-off frequencies are 1.33 kHz and 24 kHz for VLPT-gm and Delta-gm integrators, respectively. Finally, as an application example, both transconductors were used as building blocks to realize a 6th-order wavelet gm-C filter. For both approaches, THD was kept below 1% for signal swings up to 200 mVpp.The design complies with a 1.5 V supply and a 0.35 μm CMOS process and features an overall power consumption of 51 and 114 nW, respectively for VLPT-gm and Delta-gm filters.

Small size low noise amplifier with suppressed noise from gate resistance

AbstractIn this article, design and characterization results of a fully integrated 5.8 GHz low noise amplifier (LNA) using 0.13‐μm CMOS technology are presented. Commonly adopted inductive source degeneration for input impedance matching is eliminated to achieve smaller chip area while providing reasonable 50‐Ω matching. Also by adding a capacitor between the gate and the source of the input transistor, a noise source from the gate resistance is partly suppressed. The layout of the designed LNA occupies total area of 0.68 mm2 and the results show forward power gain (S21) of 12.7 dB and noise figure of 3.9 dB while consuming 6.85 mW from 1.2‐V DC supply. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 2300–2304, 2008; Published online in Wiley InterScience (www.interscience.wiley.com).DOI 10.1002/mop.23702

Design and Characterization of CMOS Avalanche Photodiode With Charge Sensitive Preamplifier

The CMOS Avalanche Photodiodes (APDs) and Charge Sensitive Preamplifiers (CSAs) were fabricated using the commercially available AMIS 0.7 mum high voltage process without any process modifications. The APDs have an N+/P-substrate structure with the diameters of their active areas equal to 25 mum, 50 mum, 100 mum, 400 mum, and 800 mum. The CSAs with three different input transistor sizes were configured with a folded cascode structure, and the ratio of the input transistor size is 1:2:4. The avalanche multiplication in APDs occurred at 10.9 V reverse bias, and gains between 9 and 40 with respect to the size of CMOS APDs were measured. In zero bias condition, the quantum efficiency peaks at 650 nm wavelength with a value of ~30%. As a result of the noise measurement for the CSAs, the CSAs with largest input transistor shows the best noise characteristics for various detector capacitances, while the CSAs with smallest size of input transistor shows the worst noise characteristics.

A Robust and Scalable Constant-$g_m$ Rail-to-Rail CMOS Input Stage With Dynamic Feedback for VLSI Cell Libraries

In this paper, we propose a robust and scalable constant- rail-to-rail CMOS input stage for VLSI cell libraries. The proposed circuit does not rely on the characteristics and particular operation (strong, moderate, and weak inversion) regions of the input transistors and is insensitive to mismatches between p- and n-channel devices. Only standard CMOS transistors are used in the circuit without any special devices, such as floating-gate or depletion-mode transistors. Very small variations (less than ) have been achieved without sacrificing the large-signal behavior. The proposed circuit is proven effective for both long-channel and deep sub-micron CMOS technologies and is suitable for VLSI cell libraries, audio/video, embedded mixed-signal system-on-chip (SoC), and other applications. A prototype amplifier with rail-to-rail input common-mode range has been designed and fabricated in a standard 0.35-m CMOS technology. Experimental results confirm the effectiveness and robustness of proposed techniques.

Low‐power fully‐differential 3.5‐GHz wideband CMOS LNA

AbstractThis article presents a low‐power fully‐differential 3.5‐GHz wideband complementary metal oxide semiconductor (CMOS) low‐noise amplifier (LNA) based on the LC‐ladder match network approach. To have low power consumption and high power gain, two common‐source stages are cascaded for reusing the bias current. To have wideband low noise figure, the gate width of the input transistor is determined from the wideband optimization of noise contribution. The implemented 0.18‐μm CMOS differential LNA achieves a power gain of 12 dB, a minimum noise figure of 3.0 dB, an input‐referred third‐order intercept point of −3.2 dBm, and a 3‐dB bandwidth of 2.5–4.5 GHz, while consuming 12.9 mW. Compared with the other wideband differential LNAs tailored for the same frequency range, a very high figure‐of‐merit of 0.36 is achieved. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 1196–1198, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23321

Display Driver IC용 Amplifier Input Transistor의 Matching 개선

The voltages for pixel electrodes on LCD panels are supplied with analog voltages from LCD Driver ICs (LDIs). The latest LDI developed for large LCD TV's has suffered from the degradation of analog output characteristics (target voltage: AVO and output voltage deviation: dVO). By the failure analysis, humps in <TEX>$I_D-V_G$</TEX> curves have been observed in high voltage (HV) NMOS devices for input transistors in amplifiers. The hump is investigated to be the main cause of the deviation for the driving current in HV NMOS transistors. It also makes the matching between two input transistors worse and consequently aggravates the analog output characteristics. By simply modifying the active layout of HV NMOS transistors, this hump was removed and the analog characteristics (AVO &dVO) were improved significantly. In the help of the improved analog characteristics, it also became possible to reduce the size of the input transistors less than a half of conventional transistors and significantly improve the integration density of LDIs.

Electron Charge Noise Minimization in 130 nm CMOS Preamplifiers

In this paper we present the design aspects for low-power, low-noise CMOS charge sensitive preamplifier that uses a leakage current compensation circuit for use with radiation sensors. The preamplifier has unipolar response with the peaking time of about 45 ns and the gain about 115– 145 mV/ke. Equivalent noise charge (ENC) is less than 80 e, when the input charge is 1–20 ke and the sensors capacitance is equal to 30 fF. In this work we present the quality function of the charge sensitive preamplifier, which characterizes best the optimal input transistor width W , with respect to equivalent noise charge and to the power consumptions.

Figure-of-Merit-Based Area-Constrained Design of Differential Amplifiers

A new methodology based on the concept of figure of merit under area constraints is described for designing optimum performance differential amplifiers. First a figure of merit is introduced that includes the three performance parameters, namely, input-referred noise, differential dc gain, and unity-gain bandwidth. Expressions for these parameters have been derived analytically and finally arrived at an expression for the figure of merit. Next it is shown how these performance parameters vary with the relative allocation of the total available area between the input and load transistors. The figure of merit peaks at a certain value of relative area allocation in the range of 60% to 80% of the available area to the input transistors. The peak value of figure of merit is a function of area. However, it is independent of biasing current (and, therefore, power consumption) subject to the minimum current (and, therefore, a minimum power) required to keep all the transistors biased in the saturation region. The peak figure of merit and minimum power required to achieve the peak figure of merit are also plotted as a function of area. These analyses help in synthesizing optimal differential amplifier circuit designs under area constraints.

The Design of the Input Stage for the Very Front-End of the CUORE Experiment

We describe the criteria for the selection of the input transistor of the very front-end for the detector, an array of 988 macro bolometers. Each of such macro bolometer is composed of a crystal of TeO2, having a mass of 750 g, to which a thermistor is glued. Due to the very large mass of the crystals, the detector response time is very slow and limited to a few Hz. The quoted characteristic for the CUORE (Cryogenic Underground Observatory on Rare Events) detectors make it attractive a solution based on a complete room temperature operated front-end. The very important requirements of such a solution are a very small parallel and low frequency series noise. We worked to the selection of a Si JFET having a gate area and pinch-off voltage that fulfils the CUORE requirements. The selected JFET has an input gate current of less than 60 fA at 40°C (the expected operating temperature at regime). The noise at 1 Hz is about 3 nV/ \(\sqrt{\mathrm{Hz}}\) at the operating point of IDS of 0.5 mA and VDS of 0.5 V, selected for having small power dissipation. Thanks to the quoted results the limit in the energy resolution given by the preamplifier is about 10 times better than that presently achievable by the crystals tested and candidate for CUORE. The wafer from which the semi-custom JFET has been cut was previously probed. All the production consisting of 1200 JFETs pairs is already available.

A JFET-CMOS Fast Preamplifier for Segmented Germanium Detectors

A JFET-CMOS fast charge-sensitive preamplifier for germanium detectors, able to operate at cryogenic temperatures, has been designed, realized, and characterized. The monolithic part of the circuit is realized in a mature 5 V 0.8 m Si CMOS technology, which yields better performances than scaled technologies in this case. The input transistor is an external Si JFET, which can be easily replaced if necessary. The charge-to-voltage gain and the fall-time are as well set through an external RC network. The circuit works in the wide temperature range of 196 to 55 C and is able to drive a terminated coaxial cable with an exceptionally fast and clean transition. Namely, with a detector capacitance of 16 pF and a negative power supply of 3 V it is able to provide a 2.4 V pulse onto a 100 load in less than 13 ns with no ringing. The static power consumption is 8 mW excluding the JFET. The area occupancy of the integrated circuit is as little as 366275 . The noise performance with a 16 pF detector capacitance is 110 r.m.s. electrons both at room temperature and at C, at a quasi-Gaussian shaping time of 10 s. The obtained performance is adequate for gamma-ray spectroscopy and pulse-shape analysis with bulky HPGe segmented detectors.

20–850 MHz low-distortion baseband amplifier in digital CMOS process

A CMOS baseband amplifier using an open-loop architecture is presented. The eight-stage amplifier, implemented in a standard 0.13 µm CMOS technology, shows a maximum gain of 30 dB in the broadband frequency range 20–850 MHz. Each amplification stage draws 0.8 mA from a single 1.2 V power supply. The total amplifier chain shows an output referred OIP3 of 11 dBm, which can be achieved by using active loads that compensate for the nonlinear transconductance of the input transistors.

A linear current-reused LNA for 3.1-10.6GHz UWB receivers

An ultra-wide-band CMOS low-noise amplifier (LNA) employing a common-gate (CG) stage for wideband input matching is presented. This LNA utilizes the concurrent noise and distortion canceling techniques. Moreover, the current-reused technique exploiting the passive network instead of using the active and power consuming element is introduced to preserve the power consumption while contributing to the noise canceling trend. In other words, this topology is capable of canceling the noise effect of input transistor without consuming much current. Simulation results based on a 0.13µm standard RFCMOS technology shows that a power gain of 13.5dB and the noise figure of 2.7-4.2dB over the -3-dB bandwidth of 2.6-10.7GHz. With the presence of a weak inversion biased transistor, an input third-order intercept point (IIP3) of +5dBm is achieved. The power consumption is 13.5mW from a single 1.2V power supply.