Input Transistor Research Articles

Performance evaluation of an architecture for the characterisation of photo-devices: design, fabrication and test on a CMOS technology

In this report, the performance of a particular pixel's architecture is evaluated. It consists mainly of an optical sensor coupled to an amplifier. The circuit contains photoreceptors such as phototransistors and photodiodes. The circuit integrates two main blocks: (a) the pixel architecture, containing four p-channel transistors and a photoreceptor, and (b) a current source for biasing the signal conditioning amplifier. The generated photocurrent is integrated through the gate capacitance of the input p-channel MOS transistor, then converted to voltage and amplified. Both input transistor and current source are implemented as a voltage amplifier having variable gain (between 10dB and 32dB). Considering characterisation purposes, this last fact is relevant since it gives a degree of freedom to the measurement of different kinds of photo-devices and is not limited to either a single operating point of the circuit or one kind and size of photo-sensor. The gain of the amplifier can be adjusted with an external DC power supply that also sets the DC quiescent point of the circuit. Design of the row-select transistor's aspect ratio used in the matrix array is critical for the pixel's amplifier performance. Based on circuit design data such as capacitance magnitude, time and voltage integration, and amplifier gain, characterisation of all the architecture can be readily carried out and evaluated. For the specific technology used in this work, the spectral response of photo-sensors reveals performance differences between phototransistors and photodiodes. Good approximation between simulation and measurement was obtained.

A Gate-Leakage Insensitive 0.7-V 233-nW ECG Amplifier using Non-Feedback PMOS Pseudo-Resistors in 0.13-μm N-well CMOS

A fully-differential low-voltage low-power electrocardiogram (ECG) amplifier by using the nonfeedback PMOS pseudo-resistors is proposed. It consists of two operational-transconductance amplifiers (OTA) in series (a preamplifier and a variable-gain amplifier). To make it insensitive to the gate leakage current of the OTA input transistor, the feedback pseudo-resistor of the conventional ECG amplifier is moved to input branch between the OP amp summing node and the DC reference voltage. Also, an OTA circuit with a Gm boosting block without reducing the output resistance (Ro) is proposed to maximize the OTA DC gain. The measurements shows the frequency bandwidth from 7 ㎐ to 480 ㎐, the midband gain programmable from 48.7 ㏈ to 59.5 ㏈, the total harmonic distortion (THD) less than 1.21% with a full voltage swing, and the power consumption of 233 ㎻ in a 0.13 ㎛ CMOS process at the supply voltage of 0.7 V.

Design of high-linear CMOS circuit using a constant transconductance method for gamma-ray spectroscopy system

We propose a novel circuit to be applied to the front-end integrated circuits of gamma-ray spectroscopy systems. Our circuit is designed as a type of current conveyor (ICON) employing a constant- g m (transconductance) method which can significantly improve the linearity in the amplified signals by using a large time constant and the time-invariant characteristics of an amplifier. The constant- g m method is obtained by a feedback control which keeps the transconductance of the input transistor constant. To verify the performance of the propose circuit, the time constant variations for the channel resistances are simulated with the TSMC 0.18 μ m transistor parameters using HSPICE, and then compared with those of a conventional ICON. As a result, the proposed ICON shows only 0.02% output linearity variation and 0.19% time constant variation for the input amplitude up to 100 mV. These are significantly small values compared to a conventional ICON's 1.39% and 19.43%, respectively, for the same conditions.

A Switching-Based Phase Noise Model for CMOS Ring Oscillators Based on Multiple Thresholds Crossing

For a ring oscillator with an arbitrary voltage swing, core transistors in delay cells typically move between saturation and triode region This can result in the overall timing jitter being dominated by timing jitter accumulated within a particular region. Based on multiple thresholds crossing concept, a new and more accurate way of handling such region change is developed. Specifically any crossing between two such regions, prior to the actual crossing of the threshold that triggers the next stage delay cell, is treated as an internal threshold crossing. The timing jitter is then the sum (in the rms sense) of the timing jitter accumulated across multiple thresholds crossing. The model agrees to within 2 dB with measurements, on differential pair based (both replica bias and physical resistor load) and current starved inverter based ring oscillators, fabricated in CMOS. Design insights from the model show that, for a differential pair ring oscillator that is originally designed with a given voltage swing such that the input transistors can be in triode, if voltage swing is reduced so that input transistors just do not go into triode, phase noise can be improved. A 7-dB phase noise improvement on an example design using a replica bias differential ring oscillator, based on this insight, is demonstrated.

An asymmetrical sensing scheme for 1T1C FRAM to increase the sense margin

A novel asymmetrical current-based sensing scheme for 1T1C FRAM is proposed, in which the two input transistors are not the same size and a feedback NMOS is added at the reference side of the sense amplifier. Compared with the conventional symmetrical scheme in Ref [8], the proposed scheme increases the sense margin of the readout current by 53.9% and decreases the sensing power consumption by 14.1%, at the cost of an additional 7.89% area of the sensing scheme. An experimental FRAM prototype utilizing the proposed asymmetrical scheme is implemented in a 0.35 μm three metal process, in which the function of the prototype is verified.

A 5.5-mW ${+}$9.4-dBm IIP3 1.8-dB NF CMOS LNA Employing Multiple Gated Transistors With Capacitance Desensitization

A capacitance desensitization technique is proposed for a multiple gated transistors amplifier with source degeneration to relax second-order distortion contribution to a third-order intermodulation distortion (IMD3), as well as an induced-gate noise contribution to noise figure. An extra capacitance, which is added between gate and source nodes of input transistors in a parallel manner, can desensitize the contribution of second-order harmonic feedback to IMD3. The capacitance is useful for optimizing noise figure, as well by controlling the input matching network quality factor (Q), which can desensitize the induced-gate noise contribution to noise figure. The low-noise amplifier is implemented with the proposed technique using 1P6M 0.18-μm CMOS technology for 900-MHz code division multiple access (CDMA) receivers. It shows a third-order intercept point of +9.4 dBm and noise figure of 1.8 dB while consuming 5.5 mW at 1.5 V.

A 1–25 GHz GaN HEMT MMIC Low-Noise Amplifier

This letter presents an ultra-wideband low noise amplifier (LNA) using gallium-nitride (GaN) high-electron mobility transistors (HEMT) technology. A -3 dB bandwidth of 1-25 GHz with 13 dB peak power gain is achieved using a modified resistive-feedback topology. To obtain such a wide bandwidth, several bandwidth enhancement techniques are utilized. An inductor connected to the source of the input transistor ensures good input matching (|S11| <; -9 dB) across the entire bandwidth. The shunt feedback loop and the inductive source degeneration minimize all the required inductor values. This GaN HEMT LNA is believed to have the widest bandwidth among all GaN HEMT monolithic microwave integrated circuit (MMIC) LNAs reported to date. With 3.3 dB minimum noise figure (F), 33.5 dBm maximum output-referred third-order intercept point (OIP3), 20 dBm maximum output-referred 1 dB compression point (Output P1 dB), this MMIC amplifier is comparable in performance to distributed amplifiers (DAs) but with significantly lower power consumption and smaller area.

An 18.85 mW 20–29 GHz wideband CMOS low‐noise amplifier with 3.85 ± 0.25 dB noise figure and 18.1 ± 1.9 dB gain

AbstractA 20–29 GHz wideband CMOS low‐noise amplifier (LNA) with flat and low noise figure (NF), flat and high‐gain (S21), and excellent phase linearity property (group‐delay‐variation is only ±22.6 ps across the whole band) is demonstrated.To achieve flat and low NF, the size, layout, and bias of the input transistor were first optimized for minimum NF, and then the inductance of the input inductors was tuned to obtain a slightly under‐damped (flat) NF frequency response. In addition, to achieve flat and high S21 and small group‐delay‐variation, the inductive‐peaking technique was adopted in the current‐reused stage for bandwidth enhancement. The LNA consumed 18.85 mW power and achieved flat and low NF of 3.85 ± 0.25 dB, and flat and high S21 of 18.1 ± 1.9 dB over the 20–29 GHz band of interest. These are the best NF and S21 performances ever reported for a 21.65–26.65 GHz or a 22–29 GHz wideband CMOS LNA. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 2017–2020, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25380

Automatic Offset Cancellation and Time-Constant Reduction in Charge-Sensitive Preamplifiers

A circuit technique is presented which eliminates the offset at the output of charge-sensitive preamplifiers and optionally reduces the resistive reset time-constant. Offset cancellation as well as time-constant reduction are obtained with no trimming. Offset cancellation is obtained actively through a negative feedback path whose ?error? variable is the offset itself. As a result the output voltage offset is automatically eliminated, irrespective of the bias point of the input transistor and the dark current of the sensor connected to the preamplifier. Using the proposed technique in low-noise charge preamplifiers for germanium detectors typical offsets in the range 100-300 mV are reduced to ±2 mV. The noise of the preamplifier is unaffected by the offset cancellation circuit. Moreover, by insertion of an optional resistor in the proposed circuitry the decay time-constant of the preamplifier is automatically reduced by a factor of up to 10, while leaving unchanged the noise and the sensitivity of the charge preamplifier. This improves pulse separation at the preamplifier's output, which can be particularly useful for pattern recognition at high event rates. The realized offset-free circuit features an equivalent noise of 650 eV fwhm in germanium at 3 ?s shaping time, i.e. an Equivalent Noise Charge of ~ 94 electrons r.m.s. and a dynamic range in excess of 86 dB, which makes it perfectly suited for high-resolution gamma-ray spectrometry with large germanium detectors.

Design of a Low Power Low Voltage CMOS Opamp

In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1microA input bias current at 0.8 micron technology using non conventional mode of operation of MOS transistors and whose input is depended on bias current. The unique behaviour of the MOS transistors in subthreshold region not only allows a designer to work at low input bias current but also at low voltage. While operating the device at weak inversion results low power dissipation but dynamic range is degraded. Optimum balance between power dissipation and dynamic range results when the MOS transistors are operated at moderate inversion. Power is again minimised by the application of input dependant bias current using feedback loops in the input transistors of the differential pair with two current substractors. In comparison with the reported low power low voltage opamps at 0.8 micron technology, this opamp has very low standby power consumption with a high driving capability and operates at low voltage. The opamp is fairly small (0.0084 mm 2) and slew rate is more than other low power low voltage opamps reported at 0.8 um technology [1,2]. Vittoz at al [3] reported that slew rate can be improved by adaptive biasing technique and power dissipation can be reduced by operating the device in weak inversion. Though lower power dissipation is achieved the area required by the circuit is very large and speed is too small. So, operating the device in moderate inversion is a good solution. Also operating the device in subthreshold region not only allows lower power dissipation but also a lower voltage operation is achieved.

Design of A Low Power Low Voltage CMOS Opamp

In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1microA input bias current at 0.8 micron technology using non conventional mode of operation of MOS transistors and whose input is depended on bias current. The unique behaviour of the MOS transistors in subthreshold region not only allows a designer to work at low input bias current but also at low voltage. While operating the device at weak inversion results low power dissipation but dynamic range is degraded. Optimum balance between power dissipation and dynamic range results when the MOS transistors are operated at moderate inversion. Power is again minimised by the application of input dependant bias current using feedback loops in the input transistors of the differential pair with two current substractors. In comparison with the reported low power low voltage opamps at 0.8 micron technology, this opamp has very low standby power consumption with a high driving capability and operates at low voltage. The opamp is fairly small (0.0084 mm 2) and slew rate is more than other low power low voltage opamps reported at 0.8 um technology [1,2]. Vittoz at al [3] reported that slew rate can be improved by adaptive biasing technique and power dissipation can be reduced by operating the device in weak inversion. Though lower power dissipation is achieved the area required by the circuit is very large and speed is too small. So, operating the device in moderate inversion is a good solution. Also operating the device in subthreshold region not only allows lower power dissipation but also a lower voltage operation is achieved.

Electret microphone buffer circuit with significantly enhanced power supply rejection

A microphone buffer circuit being adaptable for connection to a power source is disclosed. The microphone buffer circuit includes an input transistor operably connected between an input and an output for buffering an input signal. The microphone buffer circuit includes a means for reducing power supply noise capable of being coupled to the input transistor wherein the means being operably connected to the input transistor and the power source.

The Instruments for Noise Spectroscopy

The article describes basic study of broadband noise signal application in the investigation of materials. The aim is flnd a metrology method utilizable for the research on metamaterials in the frequency range of about 100MHz to 10GHz. The instrumental equipment and other requirements are presented. This research report provides an overview of the current potentialities in the described fleld and summarizes the aspects necessary for noise spectroscopy. In the complex investigation of material structures for the micro-wave application (tensor and composite character), the properties of materials are studied by means of the classic single-frequency methods, which bring about certain di-culties in the process (1). In boundary changes with a size close to the wave-length there can occur wrong information concerning the examined objects (2,3). One of the possible ways of suppressing the negative sources of signals consists in the use of wide- band signals like white noise, and in researching into the problem of absorption in the examined material (4). These methods require a source of noise, a receiving and a transmitting antenna, and A/D conversion featuring a large bandwidth; for our purposes, the bandwidth ranged between 0Hz and 10GHz. Until recently it had not been possible to realize an A/D converter of the described speed, or devices with the above-mentioned bandwidth. Currently, high-end oscilloscopes are available with a sampling frequency of tens of Gsa/s. 2. NOISE SOURCE For UWB systems, several methods of the generation of short pulses with large bandwidth have been developed to date (5). However, these singly-iterative processes are not applicable for noise spectroscopy; in this respect, there is a need of a continuous source of noise signal (ideally of white noise) with the given bandwidth. The type of source referred to is currently being produced by certain manufacturers specialized in this fleld. Importantly, for the noise spectroscopy application we require a comparatively large output power of up to 0dB/mW; the assumed bandwidth char- acteristics range up to 10GHz. Nevertheless, at this point it is appropriate to mention the fact that there occurs the fundamental problem of flnding active devices capable of performing signal ampliflcation at this kind of high frequencies. As a matter of fact, our requirements are thus limited by the current status of technology used in the production of commercially available devices; the highest-ranking solution for the bandwidth of up to 10GHz can be found only up to the maximum of 0dB/mW. Our response to the above-discussed problem consisted in an attempt to produce a noise gener- ator in laboratory conditions as, in principle, this type of generator can be considered as su-cient for testing and basic measurement. In view of the price and availability of noise diodes we decided to apply thermal noise on electrical resistance as the basic source of noise. The speciflc connection is shown in Figure 1. The flrst transistor is in the CC conflguration, where we require mainly a high input impedance of the amplifler. The thermal noise at the input is given by its input parameters. The generator could operate even without a resistor at the transistor input, yet the unconnected input would cause a substantial deterioration of the stability. The second and the third transis- tors form a cascade voltage amplifler in the CE conflguration. The output impedance of the third amplifler is 50› for its matching to coaxial line. Figure 2 shows the realization of the tested noise generator; the BFP620 vf transistors were applied. This type of transistor features the characteristic of ft = 65GHz and the maximum stable ampliflcation of 11dB at the frequency of 6GHz. The overall ampliflcation of the two CE ampliflers in cascade for the output power of 0dB/mW would have to approximate the value of 10000, and there is no hf transistor available for this kind of stable ampliflcation. Therefore, for the stable noise generator we have to accept a lower output power.

A Very Low Offset Preamplifier for Voltage Measurements in the $\mu\hbox{V}$ Range

A new topology for the implementation of a very low offset voltage preamplifier is presented. The new topology employs a time-varying resistance as a probe for detecting the sign and magnitude of the equivalent input offset of an operational amplifier in a series-shunt feedback configuration and allows for continuously correcting the offset voltage by means of a proper control feedback. The most remarkable feature of the approach we propose is the fact that the offset correction can continuously be performed with the signal voltage source connected to the circuit, as its presence and magnitude do not affect the offset detection circuit. At the same time, the offset cancellation circuit has minimum effect on the output voltage of the preamplifier in the bandwidth of the signal. An actual low-offset preamplifier based on the new approach we propose has been built and tested. While employing a metal-oxide-semiconductor field-effect transistor (MOSFET) input operational amplifier with a typical input offset of 100 μV (600-μV maximum), a voltage preamplifier with a gain of 201 and an equivalent input offset voltage below 100 nV is consistently obtained, which is independent, by design, of the temperature. While characterized by these excellent performances, the system employs quite standard low-cost components and does not require any calibration procedure.

The Effects of Elevated Temperature on Pulsed-Laser-Induced Single Event Transients in Analog Devices

We present results of laser-induced analog SETs at elevated temperatures. We found increasing pulse widths with increasing temperature for the LM124. We also observed increasing pulse amplitudes with increasing temperature for several sensitive transistors in the LM139. However the response from the input transistor was a rapidly shrinking SET, suggesting that the SET threshold increases at elevated temperatures for the input stage transistors. In addition we observed increases in the SET leading edge fall times with increasing temperature for the LM139 that are consistent with independently measured slew rates. Simulations revealed that the dominant mechanism is bipolar current gain enhancement at elevated temperatures. These temperature-induced changes to the SETs may have critical implications for radiation hardness assurance.

An ultralow noise preamplifier for low frequency noise measurements

Low frequency noise measurements are among the most sensitive tools for the investigation of the quality and of the reliability of semiconductor devices. The sensitivity that can be obtained depends on the background noise of the low noise preamplifier coupled to the device under test (DUT) that, at very low frequencies, is dominated by flicker noise. The low frequency noise produced by the DUT, on the other end, is very often the most interesting signal to be detected and analyzed. In this work we propose a very simple topology for the realization of a general purpose low noise preamplifier whose noise performances, at very low frequencies (below 10 Hz), are significantly better than those that can be obtained by the most popular commercial instrumentation. Indeed, a gain of 80 dB with a pass band extending from a few tens of mHz up to a few kHz with an equivalent input voltage noise as low as 14 nV/square root(Hz) (100 mHz), 1.4 nV/square root(Hz) (1 Hz), 1.0 nV/square root(Hz) (10 Hz), and 0.8 nV/square root(Hz) (1 kHz) are consistently obtained by using quite standard electronic components and with no need for trimming and/or calibration steps. Moreover, the junction field-effect transistor input stage of the amplifier is characterized by an equivalent input current noise below 4 fA/square root(Hz) in the entire bandwidth, resulting in negligible background noise degradation for DUT impedances in excess of 100 kohms.

Low-Voltage Tunable Pseudo-Differential Transconductor with High Linearity

A novel tunable transconductor is presented. Input transistors operate in the triode region to achieve programmable voltage-to-current conversion. These transistors are kept in the triode region by a novel negative feedback loop which features simplicity, low voltage requirements, and high output resistance. A linearity analysis is carried out which demonstrates how the proposed transconductance tuning scheme leads to high linearity in a wide transconductance range. Measurement results for a 0.5 μm CMOS implementation of the transconductor show a transconductance tuning range of more than a decade (15 μA/V to 165 μA/V) and a total harmonic distortion of −67 dB at 1 MHz for an input of 1 Vpp and a supply voltage of 1.8 V.

A novel highly accurate current mirror

A novel complementary metal-oxide semiconductor (CMOS) current mirror that can work in weak and strong inversion is proposed. The mirror is capable of accurately copying current in the nano-ampere range. The proposed scheme eliminates the DC matching error caused by the difference between drain-to-source voltages of both the input and output transistors. The proposed circuit was verified using ORCAD simulator in 0.8 μm CMOS process technology. Simulation results confirm the functionality and accuracy of the circuit.

Single-Electron-Based Flexible Multivalued Exclusive-or Logic Gate

By using two symmetrical sidewall gates, we implemented a Si-based single-electron exclusive- OR (XOR) gate and reported on the first flexible multivalued (MV) functionality. A grayscale contour plot of the output voltages displays alternating high/low values as a function of two single-electron transistor (SET) input voltages. Their voltage transfer characteristics display typical XOR or XNOR gate function depending on input voltages for binary, MV, and binary-MV mixed-modes. This flexible two-input XOR gate, combined with the previously reported NAND/NOR gates, provide three basic arithmetic blocks for the SET-based MV logic gate family.

A 0.1–20 GHz Low-Power Self-Biased Resistive-Feedback LNA in 90 nm Digital CMOS

In this letter, a 0.1-20 GHz low-power low noise amplifier (LNA) is presented. A novel self-biased resistive- feedback topology is proposed. Two inductors inside the feedback loop and a shunt-peaking inductor are exploited to extend the bandwidth. A PMOSFET with inductive degeneration is chosen as the load to boost the gain while maintaining low noise figure (NF) at high frequencies. A source-degeneration inductor is also introduced at the input transistor to ensure good input matching and stability over the entire bandwidth. All inductors are small due to the presence of feedback. The LNA was fabricated using a digital 90 nm CMOS process with 12.7 dB peak power gain, 3.3 dB minimum NF, and - 1 dBm peak input-referred third-order intercept point (IIP3). With 12.6 mW power consumption and 0.12 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area, this wideband LNA may replace distributed amplifiers (DAs) in many applications.