Design of A Low Power Low Voltage CMOS Opamp

Ratul Kr Baruah

doi:10.5121/vlsic.2010.1101

Abstract

In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1microA input bias current at 0.8 micron technology using non conventional mode of operation of MOS transistors and whose input is depended on bias current. The unique behaviour of the MOS transistors in subthreshold region not only allows a designer to work at low input bias current but also at low voltage. While operating the device at weak inversion results low power dissipation but dynamic range is degraded. Optimum balance between power dissipation and dynamic range results when the MOS transistors are operated at moderate inversion. Power is again minimised by the application of input dependant bias current using feedback loops in the input transistors of the differential pair with two current substractors. In comparison with the reported low power low voltage opamps at 0.8 micron technology, this opamp has very low standby power consumption with a high driving capability and operates at low voltage. The opamp is fairly small (0.0084 mm 2) and slew rate is more than other low power low voltage opamps reported at 0.8 um technology [1,2]. Vittoz at al [3] reported that slew rate can be improved by adaptive biasing technique and power dissipation can be reduced by operating the device in weak inversion. Though lower power dissipation is achieved the area required by the circuit is very large and speed is too small. So, operating the device in moderate inversion is a good solution. Also operating the device in subthreshold region not only allows lower power dissipation but also a lower voltage operation is achieved.

Highlights

Silicon technology continues to scale to ever smaller transistor sizes to reach the market need to include more and more transistors in DRAM and faster processing of microprocessor
In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1uA input bias current at 0.8 um technology using non conventional mode of operation of MOS transistors and whose input is depended on bias current
As the transistors are operated at weak and moderate inversion of MOS transistor, the opamp operates at low power as well as low voltage

Summary

INTRODUCTION

Silicon technology continues to scale to ever smaller transistor sizes to reach the market need to include more and more transistors in DRAM and faster processing of microprocessor. For CMOS analog circuits, when the transistors operate in weak inversion region, gm/ID reaches the maximum [6]; the minimum power consumption can be achieved due to the small quiescent current at the expense of large silicon area and slow speed. When MOS transistors operate in strong inversion, good frequency response and small area are obtained, non-optimum larger power is consumed, and VDS (sat) is high. It seems a painful tradeoff question between high speed and low power [7]. As the transistors are operated at weak and moderate inversion of MOS transistor, the opamp operates at low power as well as low voltage

PRINCIPLE

Simulated Results Circuit operating conditions

Simulated Curves

CONCLUSIONS