Low power aware standard cells using dual rail multi threshold null convention logic methodology

Abstract

Over the last few decades, low power design has become unease in VLSI design, particularly for movable and high performance systems. Power dissipation is crucial for deep sub – micron technologies. There is a need for efficient leakage diminution techniques to minimize MOS leakage currents. Reduced leakage currents extend the life of all battery operated devices like mobiles, laptops. To reduce the power dissipation in digital VLSI design, we use different types of techniques. Compared to bipolar technology, CMOS technology provides low power dissipation. But, still this topology suffers with high leakage and dynamic power consumption. These hiccups can be overcome by making use of multi-threshold and asynchronous methodologies into the conventional CMOS technology. In this paper, we investigate the performance of various threshold templates and combinational circuits using various low power and asynchronous topologies. Latest topologies like Multi Threshold CMOS (MTNCL) and Multi Threshold Null Convention Logic (MTNCL) are compared with existing CMOS technology in terms of constrains like power dissipation, delay, slew rate and energy performance.