Input Transistor Research Articles

A sub-mW 2.9-dB noise figure Inductor-less low noise amplifier for wireless sensor network applications

In this paper, a low power differential inductor-less Common Gate Low Noise Amplifier (CG-LNA) is presented for Wireless Sensor Network (WSN) applications. New Shunt feedback is employed with noise cancellation and Dual Capacitive Cross Coupling (DCCC) techniques to improve the performance of common gate structures in terms of gain, Noise Figure (NF) and power consumption. The shunt feedback path boosts the input conductance of the LNA in current reuse scheme. Both shunt feedback and current reuse bring power dissipation down considerably. In addition, the positive feedback is utilized to cancel the thermal noise of the input transistor. The proposed LNA is designed and simulated in 0.18 µm TSMC CMOS technology. Post layout Simulation results indicate a voltage gain of 16.5 dB with −3 dB bandwidth of 100 MHz–3 GHz. Also third order Input Intercept Point (IIP3) is equal to + 1 dBm. The minimum NF is 2.8 dB and the value of NF at 2.4 GHz is 2.9 dB. S11 is better than −13 dB in whole frequency range. The core LNA consumes 985 µW from a 1.8 V DC voltage supply.

A low-power low-noise and high swing biopotential amplifier in 0.18 µm CMOS

In this paper, a low-power, low-noise and high swing capacitively coupled instrumentation amplifier for biomedical applications is proposed. It uses the folded cascode operational transconductance amplifier (FC-OTA) with current scaling at the output branch to reduce the noise. To overcome the reduction in the effective transconductance of the OTA due to current scaling, series–series and shunt–shunt feedback techniques are proposed at the folded node of the FC-OTA and the composite transistor is proposed at the bottom current source of the FC-OTA. An optimization procedure is also proposed for sizing the input transistors of the FC-OTA to obtain better noise-power tradeoff. To assess the efficacy of these techniques, a biopotential amplifier is designed in 0.18 µm CMOS process and it is studied through simulation. From this study, it is found that the proposed amplifier has a 1.5–22 times and 1.4 times higher input swing and output swing respectively compared to those reported in literature. It has a gain of 39.75 dB, a bandwidth of 0.3 Hz–4.4 kHz and a total input-referred noise of 3.19 µVrms integrated over 1 Hz–10 kHz. The power consumption of the amplifier is 4.07 µW at a VDD of 1.8 V. It achieves a noise efficiency factor of 2.78, and provides input and output signal swings of 14.86 mVpp, and 1.38 Vpp respectively at THD of 1%.

A 1-GHz 1.6-mW Auto-Calibrated Bit Slicer for Energy/Envelope Detection Receivers

This brief describes a high-speed auto-calibrated bit slicer for energy and envelope detection receivers. For robust bit decision, a digital-assisted calibration method with auto threshold estimation and auto phase acquisition is employed. The bit slicer consists of a phase-locked loop for multi-phase clock generation and a dynamic comparator in which the bulk voltage of the input transistor is trimmed for threshold voltage control. The proposed bit slicer is implemented in 65-nm 1P9M CMOS, occupying a total area of 0.07 mm2. Experimental results show that the bit slicer achieves a sensitivity of 6.1 mV at 1 GHz and consumes 1.6 mW from a 1-V supply.

CMOS analog filter design using the Proportional Source Transconductances Integrator

This work assesses the applicability of a compact CMOS current-mode companding integrator in the design of analog continuous-time filters with high linearity. The companding integrator is based on the proportionality between the source transconductances of the input and output MOS transistors and is independent of the inversion level of the devices. The circuit has been designed in CMOS 130 nm technology with approximately 90 μm2 total active area including biasing elements. According to simulation results the integrator performs a useful frequency bandwidth of up to 4 MHz and a third order intermodulation distortion smaller than −47 dB for input amplitudes ranging from 100 nA to 1 μA. The small and large signal responses and the third order intermodulation, among other features, have also been analyzed through simulation for a fourth order low-pass filter and a sixth order bandpass filter. Performance is compared with a CMOS log-domain integrator and filter.

A current-reuse biomedical amplifier with a NEF < 1

Noise Efficiency Factor (NEF) is the most employed figure of merit to compare different low-noise biomedical signal amplifiers, taking into account current consumption, noise, or bandwidth trade-offs. A small NEF means a more efficient amplifier, and was assumed to be always NEF > 1 (an ideally efficient single BJT amplifier). In this work current-reuse technique will be utilized to exceed this limit in a very efficient CMOS amplifier. A micro-power, ultra-low-noise amplifier, aimed at electro-neuro-graph signal recording in a specific single-channel implantable medical device, is presented. The circuit is powered with a standard medical grade 3.6 V(nom) secondary battery. The amplifier input stage stacks twelve differential pairs to maximize current-reuse. The differential pair stacking technique is very efficient: allows most of the energy to be dissipated in the input transistors that amplify and not in mirror or bias transistors, and allows also the input transistors to operate with a reduced VDS just above saturation. The amplifier was implemented in a 0.6 μm technology, it has a total gain of almost 80 dB, with a 4 kHz bandwidth. The measured input referred noise is 4.5 nV/Hz1/2@1 kHz, and 330 nVrms in the band of interest, with a total current consumption of only 16.5 μA from the battery (including all the 4 stages and the auxiliary circuits). The measured NEF is only 0.84, below the classic NEF = 1 limit.

Low-Power Front-End ASIC for Silicon Photomultiplier

Thanks to its compact structure, mechanical endurance, and low bias voltage, the silicon photomultiplier (SiPM) can be used in small-size applications which require reduced power consumption. In order to detect the light intensity as low as a single photon, the front-end electronics has to amplify and shape the signal of the photodetector. The low-power design cannot impair the performance of readout electronics or limit the capabilities of the SiPM itself. This paper presents a two-channel integrated circuit (IC) designed in Austria Mikro Systeme CMOS 350-nm technology dedicated for the SiPM-based applications. The input stage is a super-common-gate architecture. Each channel of the IC consists of an amplifier and a peak detector with an offset reduction circuit. The power consumption of the single channel is less than 3 mW from the single voltage supply (3.3 V). Moreover, the number of channels of the IC can be easily increased thanks to small dimensions of the circuit. This paper presents a detailed analysis of the IC including: noise performance with adjustment of the input transistor’s size, transient and dc simulations of the amplifier and the peak detector, and the introduction of a simple offset reduction technique for the peak detector. The measurement results obtained with two SiPM detectors are presented.

CMOS Bulk-Controlled Fully Programmable Neuron for Artificial Neural Networks

ABSTRACTIn this paper, the design procedure of a novel neuron is discussed. Starting from the activation function circuit which is based on the modification of regulated cascode structure, a new scheme is presented which can produce the logistic function with high percentage of accuracy. The main advantage of the proposed function generator circuit is its full programmability feature in which its output waveform slope can easily be adjusted by means of the control voltages applied to the bulks of input stage metal oxide semiconductor (MOS) transistors. Also, the output waveform can easily be converted to a step function with the help of bias changes for the input transistors. Following the concepts of the previous work by the authors, the designed activation function has a good compatibility with the employed synapse. Low power and small active-area consumption are the other features of the proposed circuit which qualify it for hardware implementation of neural networks. Post-layout simulation results based on complementary metal-oxide-semiconductor (CMOS) 0.18 µm twin-tub fabrication standard process depict the correct behaviour of the designed circuits and demonstrate 96% accuracy for the proposed activation function structure. The power dissipation of the activation function circuit is 72 µW at the worst case for 1.8 power supply voltage.

A Low-Power Low-Noise Decade-Bandwidth Switched Transconductor Mixer With AC-Coupled LO Buffers

In this paper, a modified switched transconductor mixer structure is proposed to realize a low-power, low-noise, and wideband mixer, in which, a transconductor stage with fixed dc operating point is switched by the ac-coupled local oscillator (LO) signal. In this way, only a small LO signal is required to turn the transconductor ON and OFF, and thus a low-power LO buffer can be used to achieve wideband down-conversion. To further expand the bandwidth, the inductive peaking technique is used at the RF port to eliminate the capacitive loading effect resulted from the input transistors. As the noise power from LO stage appears in common mode at the mixer output, good noise performance is realized, too. Additionally, output distortion-cancellation IF buffer is added to facilitate the testing. Fabricated in the 0.13- $\mu \text{m}$ CMOS process, 15.5–17.5-dB gain and 4–5.2-dB noise figure are achieved in 1–10-GHz bandwidth. The mixer core consumes a low power of 8.3 mW from 1.5-V supply, and the whole chip consumes 22.3 mW, including the IF buffer. The active chip area is less than 0.2 mm2.

Двухканальный драйвер силовых ключей с параллельным резонансом в цепи затвора

The well-known scheme of a one-channel power switch driver with parallel resonance in gate circuit (PRD) is considered and its merits and demerits in comparison with the standard drivers are given. A new type of PRD drivers for control of FETs, combined and composite transistors is proposed and described. The proposed driver performs opposite-phase control of two MOSFETs with induced channels and can be used in advanced static converters of a megahertz frequency range. The two-channel PRD driver has a number of advantages over the previously proposed driver schemes. In comparison with traditional drivers it allows significantly smaller gating losses and a higher switching frequency to be achieved. In comparison with quasi-resonant circuits, the two-channel PRD opens the possibility to have a considerably lower power and cost of the semiconductor amplifier. In comparison with one- channel drivers better performance characteristics and more stable operation were obtained owing to the use of a resonant-circuit three-winding coil and mutual compensation of the nonlinearity of the transistors’ input capacitances. The above-mentioned nonlinearity is compensated due to the transistor input capacities being connected in coupled resonant circuits in an opposite-phase manner. As a result, a close to a sine wave shape of the gate voltage is obtained. The duty cycle for each switch is a little bit smaller than 0.5. The use of the proposed scheme guarantees that a dead interval of time is secured between the opening instants of switches controlled by a single driver and that the system will have high noise immunity. On the other hand, the two-channel PRD driver has certain shortcomings: it features a fixed duty cycle, a comparatively long switching time, and a noticeable influence of the power circuit parameters on the system operation. In view of these circumstances, it is recommended to use PRD drivers in megahertz frequency range resonance converters with phase and discrete control modes. The functional diagram of a bridge converter with phase control and two-channel PRD drivers is presented, and recommendations on selecting its elements are given. The proposed drivers are supposed to be used mainly for constructing compact converters with a high specific power for portable devices and for electric vehicles.

2.5 Gbit/s Optical Receiver Front-End Circuit with High Sensitivity and Wide Dynamic Range

AbstractAn optical receiver front-end circuit is designed for passive optical network and fabricated in a 0.18 um CMOS technology. The whole circuit consists of a transimpedance amplifier (TIA), a single-ended to differential amplifier and an output driver. The TIA employs a cascode stage as the input stage and auxiliary amplifier to reduce the miller effect. Current injecting technique is employed to enlarge the input transistor’s transconductance, optimize the noise performance and overcome the lack of voltage headroom. To achieve a wide dynamic range, an automatic gain control circuit with self-adaptive function is proposed. Experiment results show an optical sensitivity of –28 dBm for a bit error rate of 10

Analysis of Sensitivity and Power Consumption of Chopping Techniques for Integrated Capacitive Sensor Interface Circuits

In this paper, parameters related to the sensitivity of the interface circuits for capacitive sensors are determined. Both the input referred noise and capacitance of the input transistors are important for capacitive sensitivity. Chopping is an effective technique for signal conditioning circuits because of its capability of reducing circuit noise at low frequencies. The capacitive sensitivity and power consumption of various chopping techniques including the dual chopper amplifier (DCA), single chopper amplifier (SCA) and two-stage single chopper amplifier (TCA) are extracted for different values of total gain and sensor capacitance. The minimum sensitivity for each technique will be extracted based on the gain and sensor capacitance. It will be shown that designation of the amplifier and distribution of gain in the TCA and DCA are important for sensitivity. A design procedure for chopper amplifiers that illustrates the steps required to achieve either the best or the desired sensitivity while minimizing power consumption will be presented. It will be shown that for a small sensor capacitance and large total gain, the DCA has the best sensitivity, while for a large sensor capacitance and a lower gain, the SCA is preferable. The TCA is the desired architecture for an average total gain and a large sensor capacitance. Moreover, when the power consumption is the key requirement and the maximum sensitivity is not the goal; the TCA works best due to its potential to decrease the power consumption.

Design Approach for Implementation of Class-J Broadband Power Amplifiers Using Synthesized Band-Pass and Low-Pass Matching Topology

A new synthesis method for the design of broadband impedance matching network has been introduced to match the transistor input. The proposed matching network would be a realistic alternative to those that are frequently designed in low-pass structure. Easy-to-use design equations are given for this filter-based matching network. The required impedance of the stubs and the connecting lines can be directly calculated from the equations. This synthesis method simplifies the implementation of the network in the distributed form as compared with the LC low-pass matching network where equivalences are necessarily required in the rough conversion from lumped-to-distributed elements. The high-efficiency mode of operation is guaranteed by the constructed output low-pass matching network, since the LC low-pass network can provide the prescribed load terminations at fundamental frequencies and at harmonics. A commercially available 10-W GaN HEMT device (CGH40010) was used in this investigation. The proposed broadband power amplifier exhibits band-pass Chebyshev response in S-parameter measurements, and yields good gain flatness (±0.5 dB) and input return loss (>13 dB). Power-added efficiency of 58%-72% has been measured in large-signal measurements. After digital predistortion, the measured adjacent channel leakage power ratio is below -50 dBc at ±5- and ±10-MHz offset, when driven by 5- and 10-MHz WCDMA signals at 7-dB power back off.

The design and analysis of dual control voltages delay cell for low power and wide tuning range ring oscillators in 65 nm CMOS technology for CDR applications

In this paper three delay cell structures used in four-stage ring oscillator are evaluated. In the first structure, the control voltage is employed to the gate of PMOS transistors which are inserted in series with the input PMOS transistors. In this case the minimum power dissipation is gained. Since the control voltage is injected to the PMOS transistors parallel with input transistors, the better tuning range in higher frequency and lower phase noise is achieved. In order to make a tradeoff between the tuning range, phase noise and power dissipation, the PMOS transistors activated with the control voltage are applied to the oscillator in both the series and parallel paths. In improved structure, the oscillator works in 2.65–13.93 GHz under 1 V supply voltage in 65 nm CMOS technology. The phase noise is −94.33 dBc/Hz at 1 MHz offset from 3.7 GHz center frequency, while the power dissipation is 328.6 μW and the chip area is 139.5 µm2.

Efficiency enhancement by employing the transistor nonlinear capacitors effects in a 6W hybrid X-band Class-J power amplifier

This article presents the design and fabrication of a 6 W X-band hybrid Class-J power amplifier (PA) based on a bare die GaN on SiC HEMT by accurate implementing the transistor nonlinear capacitor effects. The transistor input capacitor is precisely modelled and its nonlinearity effects on Class-J performance is studied for the first time. It is shown that the harmonic generation property of the nonlinear input capacitor, especially at the second harmonic, can be of benefit to shape the transistor gate voltage as a quasi-half wave sinusoidal waveform and consequently, it can improve the power added efficiency (PAE). A complete 3D thermal model of the power transistor is developed using ANSYS software and it is calibrated based on the thermal measured data. The PA achieves 13 dB average power gain over the frequency range of 8.8-9.6 GHz. The drain efficiency and PAE are about 67% and 58% at 9.2 GHz, respectively.

An Accurate CMOS Interface Small Capacitance Variation Sensing Circuit for Capacitive Sensor Applications

In this paper, an accurate front-end CMOS interface circuit for sensing very small capacitance changes in capacitive sensors is presented. The proposed structure scales capacitance variation to the sensible impedance changing. The scaling factor of the circuit can be easily tuned by adjusting bias points of the transistors. In order to cancel or decrease the parasitic components, the RC feedback and input transistor cascading techniques are employed in the design. To simulate the circuit, HSPICE simulator is utilized to verify the validity of the theoretical formulations in 0.18 $$\upmu \hbox {m}$$μm technology. According to schematic and post-layout simulation results, input impedance changes linearly versus capacitance variations up to 0.7 GHz, while the sensor capacitance changing is varied between 0 and 200 fF. According to the simulation results, total dc power consumption is obtained as low as 1 mW with 0.9 V power supply.

A Low-Noise Charge Amplifier for the ELENA Trajectory, Orbit, and Intensity Measurement System

A low-noise head amplifier has been developed for the extra low energy antiproton ring beam trajectory, orbit, and intensity measurement system at CERN. This system is based on 24 double-electrode electrostatic beam position monitors installed around the ring. A head amplifier is placed close to each beam position monitor to amplify the electrode signals and generate a difference and a sum signal. These signals are sent to the digital acquisition system, about 50 m away from the ring, where they are digitized and further processed. The beam position can be measured by dividing the difference signal by the sum signal while the sum signal gives information relative to the beam intensity. The head amplifier consists of two discrete charge preamplifiers with junction field effect transistor (JFET) inputs, a sum and a difference stage, and two cable drivers. Special attention has been paid to the amplifier printed circuit board design to minimize the parasitic capacitances and inductances at the charge amplifier stages to meet the gain and noise requirements. The measurements carried out on the head amplifier showed a gain of 40.5 and 46.5 dB for the sum and difference outputs with a bandwidth from 200 Hz to 75 MHz and an input voltage noise density lower than $400~\text {pV}/\surd \text{Hz}$ . Twenty head amplifiers have been already installed in the ring and they have been used to detect the first beam signals during the first commissioning stage in November 2016.

Low-Power Low-Noise Pseudo-Open-Loop Preamplifier for Neural Interfaces

In this paper, we present a low-power, low-noise fully differential pseudo-open-loop preamplifier with programmable bandwidth for monitoring neural activities. The proposed pseudo-open-loop topology can achieve high-power-noise efficiency as well as high linearity and precise gain control over process. The proposed fully differential preamplifier can balance the common mode of the differential outputs without a common-mode feedback circuit, and bias the ac-coupled input transistors without an external reference. A current-ratio gain design can set a stable gain over process and bias current variations. A programmable embedded $g_{m}-C$ low-pass filter (LPF) can be tuned by adjusting bias current, so that the proposed preamplifier can be configured to be used in recording single neuron spikes or field potentials (EEG, ECoG). The proposed amplifier is configured to consume 400 nA at 2.5-V power supply; the total chip area is 0.189 mm2. The measured thermal noise floor is 85 nV/ $\surd $ Hz and input-referred noise is $1.69~\mu \text{V}_{\mathrm {rms}}$ from 0.3 Hz to 1 kHz when using a chopper stabilization technique to suppress 1/f noise. The fabricated preamplifier shows a noise efficiency factor of 2.43 in the fully differential topology.

Analysis of harmonic contents of switching waveforms emitted by the ultra high speed digital CMOS integrated circuits for use in future micro/nano systems applications

In this paper we outline the influence of transistor model quality and input signal on the estimates of higher order harmonic contents of switching waveforms emitted by the high performance and low power digital integrated circuits. Accurate estimates of higher order harmonic contents are essential in the design and development of highly integrated wireless communication systems. Harmonic contents are used to design tapered buffer chains, but the design quality is influenced by the device model discontinuities. We used Cadence Spectre and Matlab to analyze the spectrum of different flip flop and latch structures. They showed steep spectrum roll-off after the knee frequency. As a concrete example, various kinds of latches and flip-flops, which have the fastest switching capability, are evaluated by using BIM3v3 and BSIM4 transistor models.

Analysis and design of highly linear triode‐mode based OTA and its application to a wide tunable Gm‐C filter

SummaryIn this paper, a new highly linear operational transconductance amplifier (OTA) based on triode‐mode input transistors is introduced. An analysis based on theoretical relations and simulation results is presented that aims to obtain the best operating points of triode‐mode and cascode transistors to achieve the highest linearity. The proposed analysis is utilized to design a linear pseudo‐differential OTA, benefiting a linear common mode feedforward and an appropriate common mode feedback circuit. The common mode feedforward circuit is also regulated in the same manner as main the transconductor to stabilize the output common mode voltage during tuning action and achieve higher common mode rejection ratio. Proposed OTA is used to implement a tunable low‐power linear Gm‐C filter. The cutoff frequency of the filter is tunable from 2.7 to 44 MHz while its power consumption changes from 3.5 to 8.5 mW in the entire tuning range. By applying input voltages up to 1.1 Vp‐p, the filter's IM3 remains less than −48 dB for various cutoff frequencies. The proposed OTA and filter are simulated in 0.18‐μm CMOS technology with Hspice simulator. Copyright © 2017 John Wiley & Sons, Ltd.

Design and Analysis of CMOS LNAs with Transformer Feedback for Wideband Input Matching and Noise Cancellation

This paper presents a new transformer-feedback technique for RF and millimeter-wave (mmW) low-noise amplifiers (LNAs). The working principle of conventional LNAs using transformers is analyzed to show their underlying performance trade-off between input matching and noise figure (NF). To mitigate this issue, a new feedback technique is developed by constructing a drain-to-gate feedback path around the input transistor with a transformer and then further demonstrated by two LNA prototypes. In the first LNA aiming for software-defined radio (SDR) applications, the proposed technique not only achieves wideband input matching but also enables noise cancellation through an auxiliary out-of-phase forward path. Fabricated in 0.13- $\mu \text {m}$ CMOS, the LNA measures voltage gain >14 dB, minimum NF of 1.8 dB, IIP3 of 1.8–3.8 dBm, and S11 $\text{S}_{{11}}$ remains below −10 dB from 49.5 to 67 GHz.