Design and Characterization of CMOS Avalanche Photodiode With Charge Sensitive Preamplifier

Abstract

The CMOS Avalanche Photodiodes (APDs) and Charge Sensitive Preamplifiers (CSAs) were fabricated using the commercially available AMIS 0.7 mum high voltage process without any process modifications. The APDs have an N+/P-substrate structure with the diameters of their active areas equal to 25 mum, 50 mum, 100 mum, 400 mum, and 800 mum. The CSAs with three different input transistor sizes were configured with a folded cascode structure, and the ratio of the input transistor size is 1:2:4. The avalanche multiplication in APDs occurred at 10.9 V reverse bias, and gains between 9 and 40 with respect to the size of CMOS APDs were measured. In zero bias condition, the quantum efficiency peaks at 650 nm wavelength with a value of ~30%. As a result of the noise measurement for the CSAs, the CSAs with largest input transistor shows the best noise characteristics for various detector capacitances, while the CSAs with smallest size of input transistor shows the worst noise characteristics.