Input Transistor Research Articles

Design of a broadband LNA with multifunction Circuitry based on composite right /left handed transmission lines for impedance matching and suppression of unwanted frequencies

This article presents a low-noise amplifier based on the use of a composite right-left handed transmission line consisting of a single microstrip line and a split ring resonator at the transistor input and output. This design ensures optimum matching over a wide frequency range while eliminating an unwanted frequency band. The circuit is designed to operate at a center frequency of 2.4 GHz while simultaneously eliminating the frequency band around 4.8 GHz, meeting key performance criteria including improved gain, better stability, and significant noise reduction. To achieve these objectives, the transistor used undergoes precise biasing via a DC power supply. In this process, a specifically selected capacitor is arranged in series with a λ/4 transformer. This transformer, in turn, is connected in series to a radial line section. The dimensions of the proposed amplifier are 70 × 34 mm2.For validation purposes, the proposed method was implemented through design, manufacture, and testing. The results obtained show that the proposed low noise amplifier achieves a high gain of 15.27 dB, an input reflection loss S11 of −16.26 dB, an output reflection loss S22 of −13.94 dB, and an inverse isolation S12 of −22.82 dB at 2.4 GHz, with a resonance peak at 4.8 GHz allowing the surrounding frequency band to be eliminated with an attenuation of 77 dB at 4.8 GHz. What's more, the noise figure is kept below 2 dB, with unconditional stability in the desired frequency band.

Characteristics of 2N4416 Si JFETs for radiation spectrometer charge sensitive preamplifiers

The input transistors (JFETs) of feedback resistor-less charge sensitive preamplifiers (CSPs), for photon and charged particle counting radiation spectrometers, that use semiconductors as their detectors, are operated in an unusual forward biased mode; consequently, manufacturer datasheets cannot necessarily be relied upon, as they do not specify the characteristics of the JFETs when they are operated with the gate-to-source junction forward biased. This experimental study, in which 165 2N4416 and 2N4416A NJ26 silicon junction field effect transistors (JFETs) were electrically characterised at ambient laboratory temperature, focused on the JFETs’ performances in the context of their use as input transistors of feedback resistor-less charge sensitive preamplifiers (CSPs). The experimental study found evidence which supports much of the common practice of the skilled CSP designer but which had not been documented with results in the open literature until now. This includes, inter alia, that: the 2N4416 performs better than the 2N4416A; not all transistors even of the same type have comparable performance when operated in forward bias mode; only a small proportion of 2N4416 and 2N4416A transistors are of desirable performance characteristics for CSPs; and, individual screening of each candidate JFET is required if an optimally performing CSP is to be produced – even when using JFETs of the same type from the same batch. The methodology and analysis documented here will also be useful to researchers developing new wide bandgap semiconductor JFETs for high temperature tolerant and radiation-hard CSPs.

A low noise CLASS AB operational amplifier with high voltage output capability by 180 nm BCD process

Abstract In this work, a low noise CLASS AB operational amplifier, which can output high voltage, has been fabricated by a 180 nm BCD process. For the objective of achieving low noise, the bipolar junction transistor (BJT) input stage with the base current compensation structure is employed. Experimental results show that the low noise amplifier’s equivalent input current and voltage noise are 3.2 pA/sqrt (Hz) and 16.73 nV/sqrt (Hz) separately, and the rising and falling slew rates are 10.40 MV/s and 6.67 MV/s separately. With the die area of 0.629 mm2, the amplifier’s power consumption is 18.3 mW, which flows 60 μA on the 5 V low power supply and 600 μA on the 25 V high power supply.

Simple Modeling and Analysis of Total Ionizing Dose Effects on Radio-Frequency Low-Noise Amplifiers

In this study, the degradation characteristics of radio frequency (RF)-low-noise amplifiers (LNA) due to a total ionizing dose (TID) is investigated. As a device-under-test (DUT), sample LNAs were prepared using silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs) as core elements. The LNA was based on a cascode stage with emitter degeneration for narrowband applications. By using a simplified small-signal model of a SiGe HBT, design equations such as gain, impedance matching, and noise figure (NF) were derived for analyzing TID-induced degradations in the circuit-level performance. To study radiation effects in circuits, the SiGe-RF-LNAs fabricated in a commercial 350 nm SiGe technology were exposed to 10-keV X-rays to a total ionizing dose of up to 3 Mrad(SiO2). The TID-induced performance changes of the LNA were modeled by applying degradation to device parameters. In the modeling process, new parameter values after irradiation were estimated based on information in the literature, without direct measurements of SiGe HBTs used in the LNA chip. As a result, the relative contributions of parameters on the circuit metrics were compared, identifying dominant parameters for degradation modeling. For the TID effects on input matching (S11) and NF, the base resistance (RB) and the base-to-emitter capacitance (Cπ) of the input transistor were mostly responsible, whereas the transconductances (gm) played a key role in the output matching (S22) and gain (S21). To validate the proposed approach, it has been applied to a different LNA in the literature and the modeling results predicted the TID-induced degradations within reasonable ranges.

Dual-tuned high-swing variable-gain amplifier with enhanced dB-linear control

In this work, an analog-controlled variable gain amplifier (VGA) is proposed that demonstrates high linearity across a wide range of control voltages and low noise for analog front-end receivers. This work presents a dual-tuning technique utilizing diode-connected P-MOS load and pseudo-exponential approximation based source degeneration (DCPL-PESD), which enables simultaneous tuning of different control voltages to achieve the required dB-linear characteristic. The gain is increased by cross-coupling the input transistors of the differential pair. To extend the gain range, three single-stage VGAs are cascaded. The design and implementation of this VGA were carried out using the Cadence Virtuoso tool in 180 nm CMOS technology. Post-layout results indicate that the 3-stage cascaded VGA offers a gain range of 67.5 dB, of which 55 dB is dB-linear. By tuning the control voltage VC, it provides a continuous 18 dB dB-linear gain. The overall VGA consumes 0.232 mA from a 1.8 V power supply, with a power consumption of 417 μW. The bandwidth of 3-stage VGAs is measured as 46 MHz. The minimum input-referred noise (IRN) of this VGA is 4.158 nVHz. The total area, including the bias circuit and buffer, is 0.0054 mm2, and the output 1 dB compression point is −2.83 dBm at the gain of −1 dB.

The Extraction Methodic for GaN Field Transistor input Gate Capacitance in GHz Band

Authors propose new methodic for GaN field transistor input gate capacitance extraction based high-frequency S-parameters measurement and transmission line theory. Input gate capacitance was determined for GaN device (Lg = 0.25 mkm, W = 160 mkm) using proposed methodic for different operating modes at GHz band. This paper contains the dependences of the input capacitance as function of drain voltage (1.0—20.0 V) at 15.0 GHz for Vgs = —3.0 V. It was pointed that input capacitance is decreasing: 460 fF to 340 fF. This capacitance was measured using time-domain reflectometry approach in the same operating modes. Measured results were compared.

A New Low-Voltage Second Generation Voltage Conveyor Using Merged Voltage Follower and DTMOS Techniques

A very simple, compact and low-power second generation voltage conveyor circuit using only eight transistors is proposed in this work. Voltage follower stage is implemented using merged voltage follower (MVF), offering very low output impedance. A simple current mirror forms the input stage of the proposed voltage conveyor. To further enhance the linearity, another circuit is proposed where input transistor in MVF is replaced with DTMOS (Dynamic Threshold Voltage MOSFET), giving [Formula: see text][Formula: see text]mV linearity range as compared to [Formula: see text][Formula: see text]mV of the first proposal. Proposed-II VCII provides reduced offset voltage due to decreased effective threshold of DTMOS, and gain bandwidth product of the circuit also improves. Simulation results are computed using 180-nmCMOS technology with supply voltage of [Formula: see text][Formula: see text]V to validate the proposed circuits. Proposed-I and proposed-II VCII consume 85.1[Formula: see text][Formula: see text]W and 97.5[Formula: see text][Formula: see text]W, respectively. An application of the proposed conveyors as “current to voltage converter”, is also presented.

Harmonic Estimation and Comparative Analysis of Ultra-High Speed Flip-Flop and Latch Topologies for Low Power and High Performance Future Generation Micro-/Nano Electronic Systems

This paper presents estimation and analysis of the higher order harmonics, power features, and real performance of flip-flop and master-slave latch topologies. This research article outlines the impact of transistor model quality and input signal selection on the estimate of higher order harmonic contents of switching waveform emitted by the digital integrated circuits. Highly integrated systems require accurate estimation of higher order harmonics to control noise. This work presents simulations of 12 kinds of flip-flop and latch topologies on different process technologies i.e., 28 nm, 45 nm, 65 nm, and 130 nm. It is implied that the steeper the spectrum roll-off, the fewer the contents of higher order harmonics. Results of 28 nm process design kit are improved compared to 45 nm, 65 nm, and 130 nm process design kits. Furthermore, the results of the comparison of representative flip-flop and latch topologies illustrate the advantage of the approach and the suitability for high performance and low power consumption.

A Micropower Chopper CBIA with DSL-Embedded Input Stage with 0.4 V EO Tolerance for Dry-Electrode Biopotential Recording.

A chopper instrumentation amplifier (IA) dedicated for bio-potential acquisition usually requires a linearized input stage for large electrode offset voltage accommodation. This linearization leads to excessive power consumption when sufficiently low input-referred noise (IRN) is required. We present a current-balance IA (CBIA) without the need for the input stage linearization. It uses two transistors to operate as an input transconductance stage and a dc-servo loop (DSL) at the same time. An off-chip capacitor completes the DSL by ac coupling the source terminals of the input transistors via chopping switches realizing a sub-Hz high-pass cutoff frequency for dc rejection. Fabricated in a 0.35-μm CMOS process, the proposed CBIA occupies 0.41 mm2 and consumes 1.19 μW from a 3 V dc supply. Measurements show that the IA achieves an input-referred noise of 0.91 μVrms over 100 Hz bandwidth. This corresponds to a noise efficiency factor of 2.22. Typical CMRR of 102.1 dB is achieved for zero offset and degraded to 85.9 dB when a ±0.3 V input offset was applied. Gain variation of 0.5% is maintained within the range of ±0.4V input offset. The resulting performance meets well with the requirement for ECG and EEG recording using dry electrodes. A demonstration for the use of the proposed IA on a human subject is also provided.

Design and Analysis of a 4.2 mW 4 K 6–8 GHz CMOS LNA for Superconducting Qubit Readout

This article proposes a cryogenic inverter-based low noise amplifier (LNA) for qubit readout. Its input impedance matching is realized by a high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$</tex-math> </inline-formula> on-chip gate inductor and capacitive load through the gate-to-drain feedback capacitance of the input transistors. Cascode transistors are used to optimize the impedance matching, which results in a larger gate inductor and smaller load capacitor and hence a higher passive and inverter gain. Owing to the high passive gain and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$</tex-math> </inline-formula> -factor of the gate inductor at 4 K, the noise of the active stages is substantially suppressed with a negligible noise contribution of the gate inductor. Moreover, with the current re-use in the inverter topology, less power consumption is achieved for the given transconductance of transistors. The input impedance, gain, and noise analyses of the proposed LNA are performed for room temperature (RT) operation, and its noise optimization is done by taking the cryogenic operation of the devices into account. We demonstrate with the circuit analysis and measurement results that the input impedance of the LNA has a low sensitivity to variations on device parameters at cryogenic temperatures. The LNA is implemented in a 28 nm CMOS technology. It achieves 0.4–0.7 dB noise figure (NF) with 4.2 mW power consumption at 4 K, and its operating frequency is between 6–8 GHz. The LNA consumes very low power compared to the state-of-the-art cryogenic CMOS LNAs while providing similar NF performance at 4 K, which makes it suitable for dilution refrigerators.

GaN power converter and high-side IC substrate issues on Si, p-n junction, or SOI

The lateral GaN power semiconductor technology enables monolithic integration of complete power converter topologies such as half-bridges, multi-phase and multi-level converters. Fabrication on Si substrates enables low-cost and mass production. However, the operation of monolithic GaN power converters on a common conductive silicon (Si) substrate is limited compared to discrete GaN HEMTs, especially at high-voltage operation, due to substrate-biasing effects such as back-gated or trap-related static and dynamic on-resistance increase, and changed effective device capacitances. To circumvent the Si substrate related effects but still using a low-cost large-diameter Si substrate, this paper reviews isolation approaches for GaN ICs such as Si p-n junction isolation or floating Si substrates (GaN-on-Si) and buried oxide isolation using Silicon-on-Insulator substrates (GaN-on-SOI). Published GaN power converter ICs are reviewed. The effect of the isolation approaches on increased output and input transistor capacitances, influencing the switching behavior and switching loss, is calculated and compared for different voltage classes (below 100 V to 600 V-class). Finally, design guidelines for local substrate termination using the Si-based isolation approaches are discussed exemplary for a monolithic half-bridge with driver circuit. Monolithic GaN power converter integration combined with functional integration will result in a new class of advanced power converter ICs, and enable efficient, compact and low-cost power conversion applications.

A 0.15-to-0.5 V Body-Driven Dynamic Comparator with Rail-to-Rail ICMR

In this paper, a novel dynamic body-driven ultra-low voltage (ULV) comparator is presented. The proposed topology takes advantage of the back-gate configuration by driving the input transistors’ gates with a clocked positive feedback loop made of two AND gates. This allows for the removal of the clocked tail generator, which decreases the number of stacked transistors and improves performance at low VDD. Furthermore, the clocked feedback loop causes the comparator to behave as a full CMOS latch during the regeneration phase, which means no static power consumption occurs after the outputs have settled. Thanks to body driving, the proposed comparator also achieves rail-to-rail input common mode range (ICMR), which is a critical feature for circuits that operate at low and ultra-low voltage headrooms. The comparator was designed and optimized in a 130-nm technology from STMicroelectronics at VDD=0.3 V and is able to operate at up to 2 MHz with an input differential voltage of 1 mV. The simulations show that the comparator remains fully operational even when the supply voltage is scaled down to 0.15 V, in which case the circuit exhibits a maximum operating frequency of 80 kHz at Vid=1 mV.

A Compact, Low-Power, Low-NF, Millimeter-Wave Cascode LNA With Magnetic Coupling Feedback in 22-nm FD-SOI CMOS for 5G Applications

This brief presents a 2-stage, low-power, millimeter-wave (mm-wave) LNA that aims at first to reduce its passive area through a transformer formed with inductors between the gate and source sides of the input transistor in a source-degenerated cascode. While reducing the passive area, the introduced transformer creates a magnetic feedback that further reduces the LNA’s noise figure (NF). We provide a theoretical analysis of this feedback-based noise reduction method and validate it with simulations and experimental results. The LNA has been fabricated in 22-nm FD-SOI CMOS and has a core area of only 0.09 mm2. The measurement results show that this design achieves a minimum 2.1 dB NF and a maximum 23.1 dB gain between 23.7–28.5 GHz at a power dissipation of only 5.6 mW from a 0.6V supply. Furthermore, despite using only a 0.6V supply voltage, IIP3 can still reach −16.5 dBm at 28 GHz. Targeting mm-wave 5G applications, the presented LNA is among the best-in-class with a sub-1V supply voltage.

A New Tunable Gyrator-C-Based Active Inductor Circuit for Low Power Applications

A new CMOS implementation of active inductor circuit based on the gyrator-C which is suitable for low-voltage and RF applications is presented in this paper. One of the critical features of active inductors which directly affect their quality factor is their series-loss resistance. In this regard, a multi-regulated cascade stage is employed in the new structure which decreases loss. Moreover, by cascading input transistor, the transistors which determine the self-resonance frequency and quality factor will be separated from each other. This results in arranging properties of designed active inductor independently. The configuration of two-stage conventional gyrators is improved which gives the proposed design more opportunities in determining and tuning its characteristics. Also by employing common-source configuration, low conductance nodes are achieved which decrease the ohm-loss of AI. Furthermore, main properties of design can be tuned without affecting each other. The power consumption of the circuit remains as low as 0.62[Formula: see text]mW, then the circuit is suitable for low power applications. The results showed that AI is suitable for RF applications over 0.2–11.8[Formula: see text]GHz frequency range. In order to verify theoretical calculations, simulations are carried out using HSPICE and level 49 parameters (BSIM3v3) in 130[Formula: see text]nm CMOS technology. In addition, Corner and Monte Carlo analyses are considered to prove the efficiency of the circuit against the process variation.

A Large-Swing High-Linearity Fully-Dynamic Amplifier With Automatic Calibration

In high-speed pipelined successive-approximation-register (SAR) analog-to-digital converters (ADCs), the residue amplifiers dominate the overall ADC speed, power, and accuracy. To improve the ADC performance, this brief proposes a large-swing high-linearity fully-dynamic open-loop amplifier. By setting the cascode input transistors in linear region, both the input/output swing and the linearity are improved significantly. By clamping the drain voltages of input transistors, the amplifier gain is PVT insensitive. These drain voltages of input transistors are clamped through a dynamic comparator with small size, which helps save energy. The comparator offset is automatically canceled out through a novel thermal-noise-based technique. Designed in a 40nm CMOS process, the proposed amplifier achieves an output swing of 400mVpp, a settling accuracy of 8-bit ENOB, and a voltage gain of 16X, under a 100MHz clock frequency. It is fully-dynamic and only consumes 1.15mW of power under a 1.1V supply. Compared to the state-of-the-art dynamic amplifiers, the output swing is increased by 4 times; the settling accuracy is improved by 2 bits; the voltage gain is increased by 4 times; the PVT sensitivity of voltage gain is reduced by 4.7 times; and the power consumption is decreased by 45% with fully-dynamic operation.

Cryogenic front-end amplifier design for large SiPM arrays in the DUNE FD1-HD photon detection system

The photon detection system of the first far detector (FD1-HD) of the DUNE experiment will detect scintillation photons produced by particle interactions in a kiloton-scale liquid Argon time projection chamber. The photon detectors of choice are silicon photomultipliers (SiPM), 6×6 mm2 each, arranged in groups of 48, which present a significantly low impedance to the front-end electronics. This paper details the design of a cryogenic amplifier with exceptionally low white voltage noise of 0.37 nV√(Hz), based on a silicon-germanium input transistor and a BiCMOS fully differential operational amplifier. It yields excellent single photoelectron resolution even at low overvoltage values. The signal rise time is below 100 ns, and the dynamic range is about 2000 photoelectrons at the typical operating overvoltage. It draws 0.7 mA from a single 3.3 V supply, for a power consumption of 2.4 mW per channel. Simplified models were developed to predict the single photolectron signal shape and the signal to noise ratio, with a good match to measured performance.

A novel front-end amplifier for gain-less charge readout in high-pressure gas TPC

This paper presents a novel low-noise front-end amplifier manufactured in a standard 130 nm CMOS process. The front-end amplifier is part of an integrated sensor, with an array of which, forms a charge readout plane in a high-pressure gaseous Time Projection Chamber (TPC) for 0νββ search. The novel front-end amplifier composed of a source-drain follower and a common-source amplifier is proposed. The potential of both the source and drain node of the input transistor follows its gate. Hence the effective input capacitance contributed by the input transistor is significantly reduced. A hexagon charge collection electrode with a diameter of 1 mm is connected to the input node of the front-end amplifier. The shielding technique is applied and the shielding metal is connected to the source or drain node of the input transistor. Therefore, the effective input capacitance contributed by the charge collection electrode is decreased. The extraction result shows that the input capacitance is decreased from the 4 pf down to 7.4 fF. A test chip has been designed and an equivalent noise charge of 33 e− is achieved from the simulations.

Investigation of Neutron Displacement Effects in Bipolar Amplifiers With Lateral and Substrate p-n-p Input Transistors

Neutron displacement effects in LM158L and LM158V bipolar amplifiers with lateral p-n-p (LPNP) and substrate p-n-p (SPNP) input transistors, respectively, were investigated based on neutron irradiation experiments and TCAD simulation. Experimental results suggest that the type of input transistor of the amplifier has great impact on the neutron displacement degradation. The input bias current and input offset current of the amplifier with SPNP input transistor increase more than that with LPNP input transistor, and more severe degradation in SPNP than that in LPNP leads to the corresponding more severe degradation in the specific amplifier. TCAD simulations were performed to analyze the physical mechanism of neutron displacement effects in these two kinds of input transistors. For LPNP, the hole current is much closer to the surface of the silicon, however for SPNP, the hole current is much deeper into the bulk silicon, so the displacement traps in whole bulk all contribute to the total recombination. Therefore, the total recombination in SPNP is larger than that in LPNP, resulting in more severe degradation under neutron irradiation.

Miniature Wide-Band Noise-Canceling CMOS LNA.

In this paper, a wide-band noise-canceling (NC) current conveyor (CC)-based CMOS low-noise amplifier (LNA) is presented. The circuit employs a CC-based approach to obtain wide-band input matching without the need for bulky inductances, allowing broadband performance with a very small area used. The NC technique is applied by subtracting the input transistor’s noise contribution to the output and achieves a noise figure (NF) reduction from 4.8 dB to 3.2 dB. The NC LNA is implemented in a UMC 65-nm CMOS process and occupies an area of only 160 × 80 μm2. It achieves a stable frequency response from 0 to 6.2 GHz, a maximum gain of 15.3 dB, an input return loss (S11) < −10 dB, and a remarkable IIP3 of 7.6 dBm, while consuming 18.6 mW from a ±1.2 V DC supply. Comparisons with similar works prove the effectiveness of this new implementation, showing that the circuit obtains a noteworthy performance trade-off.

Detection of Proton Carriers in Tyrosine-Rich Peptide Thin Film

Traditional Von Neumann structure, where memory and computational units are separated, is now facing significant difficulties in terms of power consumption and computing speed in big data era. Therefore, human brain-like computing architecture is now paid attention in research field owing to its high parallelism, fault tolerance and robustness1-2. In this biological system, synaptic weight which plays crucial role in memory and learning is modulated by ionic species, especially protons transmitted between synapses. Here, we focused on short length peptide Y7C (YYACAYY) thin film which induces proton coupled electron transfer (PCET) due to its Tyrosine-rich structure. The Y7C film has shown an interesting behavior in which electrical conductivity varies with humidity3-4. By this modulation, bimodal memristor using both of voltage and humidity5 input and synaptic transistor which shows dynamic reponses through humidity have been demonstrated, but direct relation between current and proton conduction is still ambiguous. Therefore, we measured transient current flow between Pd and Au electrode and detected proton conduction of Y7C film.In previous studies, voltage & humidity controlled Y7C bimodal memristor has been reported. However, since the current regulation through humidity showed insufficient response than that through voltage, a definite relationship between moisture and current needs to be defined. To achieve that, thin film of the peptide material dissolved in Trifluoroacetic acid (TFA) 99% solution was spin coated on SiO2/Si substrate. By measuring the transient current of the Y7C film, presence of temporary charge carriers was observed. Also, the electrical impedance spectroscopy (EIS) of peptide layer showed a semicircle and a nonvertical tail, which indicate ionic conduction through the film. Lastly, film characterization of Y7C thin layer unveiled that the corresponding ions are protons as originally targeted. This research has showed principles of peptide thin film’s current increment driven by both of humidity and voltage through electrochemical reaction. Fig.1. Transient charge flowing through Y7C thin film measured in various atmospheric conditions and electrodes Acknowledgment This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. 2020R1A2C2004864). References Pakkenberg B, Pelvig D, Marner L, Bundgaard M J, Gundersen H J G, Nyengaard J R and Regeur L 2003 Exp. Gerontol. 38 95Abbott L F and Nelson S B 2000 Nat. Neurosci. 3 1178Lee, Jaehun, et al. "Proton conduction in a tyrosine‐rich peptide/manganese oxide hybrid nanofilm." Advanced Functional Materials 27.35 (2017): 1702185.Sung, Taehoon, et al. "Effects of proton conduction on dielectric properties of peptides." RSC advances 8.59 (2018): 34047-34055.Song, Min-Kyu, et al. "Proton-enabled activation of peptide materials for biological bimodal memory." Nature Communications 11.1 (2020): 1-8. Figure 1