3-input Majority Gate Research Articles

Design of QCA based memory cell using a novel majority voter with physical validation

Quantum Dot Cellular Automata (QCA) is a unique transistor less paradigm which effectively uses change in cell polarization to perform logical operations with high speed, low power and high intricacy. In recent years, the need of high performance memory cell is increased for improving the system performance. This paper presents the design of a QCA based memory cell with read write capabilities. In recent past, most of the QCA circuits are designed using the conventional three input majority voter. The conventional three input majority gate is not fault tolerant. Thus, we need an alternative design which can serve as the majority voter and also shows the fault tolerance. Moreover, the design of three input majority voter is not much addressed . In this paper, an alternative, simple structure of three input majority voter is presented which is better than the conventional one in terms of fault tolerance. In addition to this, the proposed three input majority voter is power aware and efficient to realize various digital circuits. The correctness of the proposed majority voter is validated through the physical proof. Moreover, the proposed gate is subjected to cell displacement defect to investigate the testability. The proposed gate is further used to implement rudimentary elements such as XOR gate, multiplexer and D latch. Finally, the design of Random Access Memory (RAM) cell with read, write, set and reset capabilities is proposed using the presented majority voter. The proposed circuits are further subjected to comprehensive analyses for estimation of cost functions and energy dissipation. The investigation of presented circuits manifests the use of proposed majority voter for next generation computing circuits.

A thermally aware performance analysis of quantum cellular automata logic gates

<span lang="EN-US">The high-performance digital circuits can be constructed at high operating frequency, reduced power dissipation, portability, and large density. Using conventional complementary-metal-oxide-semiconductor (CMOS) design process, it is quite difficult to achieve ultra-high-speed circuits due to scaling problems. Recently quantum dot cellular automata (QCA) are prosed to develop logic circuits at atomic level. In this paper, we analyzed the performance of QCA circuits under different temperature effects and observed that polarization of the cells is highly sensitive to temperature. In case of the 3-input majority gate the cell polarization drops to 50% with an increase in the temperature of 18 K and for 5 input majority gate the cell polarization drops more quickly than the 3-input majority. Further, the performance of majority gates also compared in terms of area and power dissipation. It has been noticed that the proposed logic gates can also be used for developing simple and complex and memory circuits.</span>

Design of an ultracompact 3-input majority gate using photonic crystal

Design of an ultracompact 3-input majority gate using photonic crystal

An ultra-efficient design of fault-tolerant 3-input majority gate (FTMG) with an error probability model based on quantum-dots

Quantum-dot cellular automata (QCA) has recently attracted significant notice thanks to their inherent ability to decrease energy dissipation and decreasing area, which is the primary need of digital circuits. However, the lack of resistance of QCA circuits under defects in previous works is a vital challenge affecting the stability of the circuit and output production. In addition, with the high defect rate in QCA, suggesting resistance and stable structures is critical. Furthermore, the 3-input majority gate is a fundamental component of QCA circuits; therefore, improving this essential gate would enable the development of fault-tolerant circuits. This paper recommends a 3-input majority gate which is 100% fault-tolerant against single-cell omission defects. Moreover, the fundamental gates are introduced based on the proposed gate. In addition, an adder and a 1:2 decoder are also designed. Using QCADesigner 2.0.3 and QCAPro software, simulations of structures and analysis of power consumption are performed.

Silicon microring resonator based all-optical 3-input majority gate and its applications

In this study, we propose an all-optical majority gate using silicon waveguide-based microring resonator for the first time to our knowledge. All-optical microring resonator based majority gate has attractive properties such as energy-efficient, ultra-high-speed, and compact which are essential for optical computing. We have designed different logic circuits such as AND, OR, NOR, NAND, and one-bit full adder by exploiting the majority gate with inverter circuits. Optoelectronic conversion which limits the operational speed is avoided in our design. The operational speed of our design is nearly 260 Gbps. The required pump power for switching is only 1.66 mW for micro-ring resonator based switch which is very less comparatively. These designs have been realized in MATLAB as well as in Ansys Lumerical finite difference time domain (FDTD) simulation platform. The "figure of merits" of the presented majority gate is achieved numerically through simulation. The obtained values of extinction ratio and contrast ratio are much higher for the proposed majority gate and the values are 28.11 dB and 32.88 dB, respectively. The on-off ratio is also high for single microring resonator and it is 38.2 dB.

N譔 Clos Digital Cross-Connect Switch Using Quantum Dot Cellular Automata (QCA)

Quantum dot cellular automata (QCA) technology is emerging as a future technology which designs the digital circuits at quantum levels. The technology has gained popularity in terms of designing digital circuits, which occupy very less area and less power dissipation in comparison to the present complementary metal oxide semiconductor (CMOS) technology. For designing the routers at quantum levels with non-blocking capabilities various multi-stage networks have been proposed. This manuscript presents the design of the N×N Clos switch matrix as a multistage interconnecting network using quantum-dot cellular automata technology. The design of the Clos switch matrix presented in the article uses three input majority gates (MG). To design the 4 × 4 Clos switch matrix, a basic 2 × 2 switch architecture has been proposed as a basic module. The 2 × 2 switching matrix (SM) design presented in the manuscript utilizes three input majority gates. Also, the 2 × 2 SM has been proposed using five input majority gates. Two different approaches (1&2) have been presented for designing 2 × 2 SM using five input majority gates. The 2 × 2 SM design based on three input majority gate utilizes four zone clocking scheme to allow signal transmission. Although, the clocking scheme used in 2 × 2 SM using three input MG and in 2 × 2 SM approach 1 using five input MG is conventional. The 2 × 2 SM approach 2 design, utilizes the clocking scheme in which clocks can be applied by electric field generators easily and in turn the switch element becomes physically realizable. The simulation results conclude that the 2 × 2 SM is suitable for designing a 4 × 4 Clos network. A higher order of input-output switching matrix, supporting more number of users can utilize the proposed designs.

Design, Synthesis and Assessment of QCA primitives of 5-input Majority gate in field-coupled QCA Nanotechnology

Quantum-dot Cellular Automata (QCA) is an exciting new development in the field of nanoscale-based very large scale integration (VLSI) that has the potential to replace more conventional complementary metal oxide semiconductor (CMOS) technology. In this article, a thorough and detailed description of the novel QCA based 5-input Majority gate is presented. In order to validate the accuracy of a 5-input majority gate, a comprehensive analysis has been carried out, taking into account the location of each and every QCA cell inside a structure. In this paper, a completely new 1-bit full-adder is constructed in order to assess the possible advantages offered by the recently developed 5-input majority gate. The comparative analysis with the reported designs in the literature revealed that the proposed full adder is superior in terms of cell count with a reduction of more than 54.79 %, as well as a decrease in area of more than 25 %, and a reduction in latency of 83.33 %. These findings were derived from the observation that the proposed full adder is better. For the purpose of demonstrating the usefulness and dependability of the strategy, power analysis have been carried out on the proposed full adder design using the QCAPro and QCADesigner 2.0.3 tools, respectively. The new majority gate technique is based on a variety of designs that enjoy the parameters of less area, durable circuit architecture, and optimal clock cycles, as well as the higher performance aspects associated with high-speed computation.

Design and energy analysis of a new fault-tolerant SRAM cell in quantum-dot cellular automata

Quantum-dot cellular automata (QCA) is an emerging technology proposed in response to the limitations of CMOS technology. Moreover, static RAM (SRAM) is crucial for memory design, and efficient RAM design can play a significant role. This paper proposes a fault-tolerant QCA SRAM cell based on QCA three- and five-input majority gates. This cell is implemented on a single layer and does not require any rotated cell, which significantly improves the manufacturability and robustness of the design. Furthermore, our design can tolerate a single omission fault. The proposed 3-input majority gate improves complexity, area, and energy dissipation, on average, by 54%, 68%, and 67% in 1 Ek, respectively, as compared to its previous counterparts. The proposed fault-tolerant SRAM cell improves the complexity, area, and total energy dissipation by almost 13%, 25%, and 35% in 1 Ek, respectively, as compared to its state-of-the-art QCA-based single-layer fault-tolerant counterpart.

A Defect Tolerant Design for 5-Input Majority Gate in Quantum-dot Cellular Automata

A Defect Tolerant Design for 5-Input Majority Gate in Quantum-dot Cellular Automata

Ultra-efficient adders and even parity generators in nano scale

This paper suggests a single-layer 5-input majority gate (MV5) using 11 simple cells in the Quantum-Dot Cellular Automata (QCA) technology. All simulations are performed by QCADesigner 2.0.03. Moreover, the energy consumption of the suggested 5-input majority gate is calculated using the QCAPro tool. The suggested gate shows power consumption improvements by 15.69, 9.56, and 5.95% at three levels of 0.5Ek, 1Ek, and 1.5Ek compared with the best previous designs. Moreover, using the suggested gate, n-bit QCA adder and n-bit even parity generator are designed. A comparison of the cell counts in the suggested 1-bit full-adder and the 4-bit even parity generator with the best previous structures shows 35.21% and 6.12% improvements, respectively. In addition, the suggested 4-bit and 8-bit adders show 2.29%, 4.87%, 5.76% and 24.29% improvements in terms of the cell counts compared to the best designs, respectively.

Design of a new multiplexer structure based on a new fault-tolerant majority gate in quantum-dot cellular automata

Quantum-dot cellular automata (QCA) technology is believed to be a good alternative to CMOS technology. This nanoscale technology can provide a platform for design and implementation of high performance and power efficient logic circuits. However, the fabrication of QCA circuits is susceptible to faults appearing in this form of missing cells, additional cells, rotated cells and displaced cells. Over the years, several solutions have been proposed to address these problems. This paper presents a new solution for improving the fault tolerance of three input majority gate. The proposed majority gate is then used to design 2-1 multiplexer and 4-1 multiplexer. The proposed designs are implemented in QCA Designer. Simulation results demonstrate significant improvements in terms of fault tolerance and area requirement. The proposed gate consists of 11 cells and requires an area of 0.0096 μm2. The proposed design has 100% tolerance to the fault of a single missing cell and 71.43% tolerance to the rotation of one cell. The proposed 2-1 multiplexer consists of 41 cells and requires an area of 0.066 μm2. This multiplexer has 95.24% tolerance to the fault of a single missing cell.

Multifrequency Data Parallel Spin Wave Logic Gates

By their very nature, Spin Waves (SWs) with different frequencies can propagate through the same waveguide without affecting each other, while only interfering with their own species. Therefore, more SW encoded data sets can coexist, propagate, and interact in parallel, which opens the road towards hardware replication free parallel data processing. In this paper, we take advantage of these features and propose a novel data parallel spin wave based computing approach. To explain and validate the proposed concept, byte-wide 2-input XOR and 3-input Majority gates are implemented and validated by means of Object Oriented MicroMagnetic Framework (OOMMF) simulations. Furthermore, we introduce an optimization algorithm meant to minimize the area overhead associated with multifrequency operation and demonstrate that it diminishes the byte-wide gate area by 30% and 41% for XOR and Majority implementations, respectively. To get inside on the practical implications of our proposal we compare the byte-wide gates with conventional functionally equivalent scalar SW gate based implementations in terms of area, delay, and power consumption. Our results indicate that the area optimized 8-bit 2-input XOR and 3-input Majority gates require 4.47x and 4.16x less area, respectively, at the expense of 5% and 7% delay increase, respectively, without inducing any power consumption overhead. Finally, we discuss factors that are limiting the currently achievable parallelism to 8 for phase based gate output detection and demonstrate by means of OOMMF simulations that this can be increased 16 for threshold based detection based gates.

A Novel Co-Planar Five Input Majority Gate Design in Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA) design forms a cellular alternative to the conventional CMOS design approach. In the present paper, a novel design of five input majority gate is proposed. The proposed design enjoys the features of no rotated cells, single-layer structure, and robust design. A comparative analysis of the majority gate designs reported by various researchers in the literature is also carried out. The present design exhibits a 7.69% decrease in the number of cells with an efficiency similar to the best equivalent designs reported in the literature. A full adder and an XOR gate with a cell reduction of 3.57% and 3.12%, respectively, are proposed. QCADesigner-E tool is utilized for the simulation and validation of the functionality of the suggested designs.

Area efficient in-plane nanomagnetic multiplier and convolution architecture design

In this study, we propose a nanomagnetic logic (NML) based 2 bit multiplier architecture design for the first time to the best of author’s knowledge. This complex combinational logic (nanomagnetic multiplier) design proposed is built by exploiting shape, positional hybrid anisotropy and the ferromagnetically coupled fixed input majority gate. Subsequently, we extend this proposed multiplier architecture along with the NML adder architecture in introducing NML based convolution architecture design which is efficient in terms of number of nanomagnets, majority gates and clock-cycles. The proposed NML design yields ∼21%–72%, ∼26%–42%, ∼36%–63%, and ∼20%–68%, reduction in the required number of nanomagnets, majority gate, clock cycles and energy compared to the state-of-the-art designs.

QCA based Novel Reversible Reconfigurable Ripple Carry Adder with Ripple Borrow Subtractor in Electro-Spin Technology

An important arithmetic component of “Arithmetic and Logic Unit” or ALU is reconfigured in this paper, known as “Full-Adder-Subtractor”, where an advance low-power, high-speed nano technology “QCA” with electro-spin criterion is used with reversibility and the advancement of multilayer 3D circuitry. In this modern digital world, this selected nano-sized technology is an effective alternative of widely used “CMOS Technology” because all the limitations, mainly limitation due to the presence of high power dissipation at the time of device-density increment in a “CMOS” based integrated circuit, can be optimized by “QCA” nano technology with electro-spin criterion and this technology also supports reversible logic in multilayer 3D platform with less complexity. This paper, primarily presents two novel “QCA” based 3-layered “Adder-Subtractor” designs using the collaboration of multilayer inverter gates, reversible modified 3-input Feynman-Gate and 3-input MG (Majority Gate) with very less cell-complexity, area-occupation, delay and energy-dissipation and high output-strength, temperature-tolerance and accuracy. A clear parametric investigation on presented designs are shown clearly in this paper through a comparative manner with some previous published related structures. Additionally, another parametric-experiment on a novel multibit reversible multilayer “QCA” based “Full-Adder-Subtractor” circuitry using the working phenomenon of “Ripple Carry Adder” (RCA) and multibit subtractor (“ripple borrow subtractor” or RBS) is presented in this proposed work in a proper way and this combination of RCA and multibit subtraction operation converts the proposed circuitry into a hybrid form, which is more effective compare to some other advanced adders in parametric-optimization field.

An Efficient Quantum-Dot Cellular Automata Full Adder Based on a New Convertible 7-Input Majority-Not Gate

Quantum-dot cellular automata (QCA) is one of the most promising emerging paradigms offered for substitution of ongoing MOSFET technology. In order to qualify the QCA technology, all the previously designed circuits, either combinational or sequential, have been redesigned using QCA cell interaction. In this way, adder circuits, which play the most significant role in the arithmetic structures, have been extensively explored. In this paper, in the first step, a new single-layer 7-input majority-not gate is presented. This gate can be easily converted to a 5- or 7-input majority gate to form diverse QCA circuits. The extensive energy dissipation and structural evaluations over the proposed 5-input majority gate and the best previously published ones prove its prominent performance. In the next step, this well-shaped gate is leveraged as a basilar structure for implementation of an ultra-high speed QCA full adder. With respect to the counterpart designs, our proposed one surpasses all the previously published full adders in different points of views such as computation speed and number of consumed cells. QCADesigner and QCAPro tools are used as popular simulation engines to authenticate the circuit functioning and to measure energy dissipation, respectively.

Three-Input Gates for Logic Synthesis

Most logic synthesis algorithms work on graph representations of logic functions with nodes associated with arbitrary logic expressions or simple logic functions and iteratively optimize such graphs. While recent multilevel logic synthesis efforts focused primarily on graphs with 2-input nodes such as AND and OR gates, the recently proposed paradigm of Majority-Inverter Graphs (MIGs) instead uses the 3-input Majority gate as the node function. As this technique proved to be a success, it is natural to ask: are there other 3-input gates better suited for logic synthesis? Motivated by this question, we investigate the relative advantages of 3-input gates as constituents of logic networks. We consider representative gates from each of the ten nondegenerate 3-input NPN classes and study how powerful they are at representing Boolean functions. Using SAT-based exact synthesis, we evaluate each 3-input gate using the minimum number of such gates (together with inverters) needed to synthesize all 4-input Boolean functions and a subset of frequent 5-input and 6-input Boolean functions. We show that the logic gate Dot(x,y,z) \mathrel \mathrel \mathop:= x ⊕(z Vxy) outperforms the rest in terms of expressive power. We further confirm this observation by showing that Dot-Inverter Graph representations are more than 14% smaller as compared to MIG representations of EPFL benchmarks.

실제 양자 컴퓨팅 환경에 강한 양자점 셀룰라 오토마타 기반의 내결함성 3입력 다수결 게이트 설계

양자점 셀룰러 오토마타(QCA)는 양자 컴퓨팅 환경을 구현하기 위한 차세대 나노 회로설계 기술이다. QCA로 회로를 설계하는 데 있어서 결함을 피하기란 어렵다. 내결함성이 아닌 회로는 사소한 결함에도 회로 전체의 동작에 이상이 생길 수 있다. 반면에 내결함성 회로는 회로에 발생한 결함에 저항성을 가진다. 그러나 기존의 내결함성 회로는 내결함 성능을 확보하기 위해 면적이 증가하였다. 이로 인해 내결함성 회로의 성능이 일반 회로들보다 떨어지는 문제점이 발생한다. 이에 본 논문에서는 면적 문제가 해결된 내결함성 다층구조 3입력 다수결 게이트를 제안하고, 이를 기존에 제안되었던 회로들과 비교 분석한다. 비교분석결과, 면적 면에서 최소 19.64%에서 최대 88.40%의 개선이 이루어졌음을 확인할 수 있다. 이는 차후에 다른 내결함성 회로를 설계할 때 본 논문에서 제안하는 3입력 다수결 게이트를 기본 소자로 활용하면 성능 면에서 큰 향상을 이루어낼 수 있음을 의미한다.

The Development of an Efficient 2-to-4 Decoder in Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA) is known as one of the best alternative technologies for CMOS on nano-scale dimensions, which allows the design of digital circuits with high speed and density. Decoders are considered as one of the most widely used combinational circuits. They also play an important role in designing circuits such as FPGA, CLB, and memory addressing. In this paper, we propose an effective design of the 2-to-4 decoder in the QCA technology. The proposed design consists of only three inverter gates and six 3-input majority gates. Two single-layer and three-layer of the proposed 2-to-4 QCA decoder with only 56 and 62 cells are provided and they require 3 and 4 clock cycles respectively. Also, one multi-layer 3-to-8 QCA decoder is developed and implemented using the proposed 2-to-4 QCA decoder. The proposed circuits are simulated using the QCADesigner 2.0.3 tool. A comparison of the proposed 2-to-4 QCA decoder with related designs shows that the proposed decoder has a good performance in terms of the number of cells, the occupied area, and the delay criteria. Also, the QCAPro tool is used to compute the power dissipation of the proposed decoder. Finally, the results are affirmed by physical proofs.

5-Input majority gate based optimized full adder circuit in nanoscale coplanar quantum-dot cellular automata

Quantum-dot cellular automata (QCA) is one of the alternative nanotechnologies that empower nanoscale circuit models with high performance and minimal energy depletion features. In this study, design for a 5-input majority gate (MV5) is proposed. The reported design requires a smaller number of cells, lower time delay, less design cost, and area. The precision of this 5-in MV is confirmed by the theoretical validation, and the QCADesigner simulation engine is applied for proving the majority circuit with functionality. In addition, an optimized full adder (FAd) circuit is designed to consider the appropriateness of the proposed (MV5). The outcomes exhibit that the designed full adder performs reliably well associated with contemporary multi-layer layouts, and executes well in the case of existing coplanar FAd circuits in all sides. The designed FAd obtains an improvement of 20% in terms of covered extent, 35% in cell extent, 32% in cell intricacy, 58% in delay, and 20% in cost correspondingly, as compared to its best counterpart. QCAPro, an energy valuation tool, is employed to assess the power consumption of the reported designs. The outcomes in this work corroborate that the hardware prerequisite for a QCA design is decreased, and circuits become simpler in gate counts and clock segments by considering the proposed design.