Abstract
An important arithmetic component of “Arithmetic and Logic Unit” or ALU is reconfigured in this paper, known as “Full-Adder-Subtractor”, where an advance low-power, high-speed nano technology “QCA” with electro-spin criterion is used with reversibility and the advancement of multilayer 3D circuitry. In this modern digital world, this selected nano-sized technology is an effective alternative of widely used “CMOS Technology” because all the limitations, mainly limitation due to the presence of high power dissipation at the time of device-density increment in a “CMOS” based integrated circuit, can be optimized by “QCA” nano technology with electro-spin criterion and this technology also supports reversible logic in multilayer 3D platform with less complexity. This paper, primarily presents two novel “QCA” based 3-layered “Adder-Subtractor” designs using the collaboration of multilayer inverter gates, reversible modified 3-input Feynman-Gate and 3-input MG (Majority Gate) with very less cell-complexity, area-occupation, delay and energy-dissipation and high output-strength, temperature-tolerance and accuracy. A clear parametric investigation on presented designs are shown clearly in this paper through a comparative manner with some previous published related structures. Additionally, another parametric-experiment on a novel multibit reversible multilayer “QCA” based “Full-Adder-Subtractor” circuitry using the working phenomenon of “Ripple Carry Adder” (RCA) and multibit subtractor (“ripple borrow subtractor” or RBS) is presented in this proposed work in a proper way and this combination of RCA and multibit subtraction operation converts the proposed circuitry into a hybrid form, which is more effective compare to some other advanced adders in parametric-optimization field.
Highlights
In this advance nano-technical digital world ALU or “Arithmetic and Logic Unit” is a key component of any processor and Full-Adder is an important component of ALU [8] as a part of the arithmetic unit
2 to 1 MUX is added with reversible “AdderSubtractor” design and in this paper the presented single-bit reversible “Adder-Subtractor” design is compared with our proposed multilayer reversible “Adder-Subtractor” design, which gives a multilayer multi-bit (4-bit) “AdderSubtractor” design based on the combination of Ripple Carry Adder” (RCA) and RBS
In this paper, reversible gate is chosen in multilayer platform to bring more advancement of our proposed “Adder-Subtractor” physicalformation and this multibit design of proposed advanced adder with subtraction operation is more acceptable than other advanced adder circuits, such as “Carry Look Ahead Adder” or CLA and “Carry Save Adder” or CSA [6] due to the better occupied-area, delay and energy-dissipation reduction capability of our proposed design compare to other discussed designs
Summary
In this advance nano-technical digital world ALU or “Arithmetic and Logic Unit” is a key component of any processor and Full-Adder is an important component of ALU [8] as a part of the arithmetic unit. Electro-Spin criterion based “Quantum-Dot Cellular Automata” or “QCA” technology is mainly used to form physical level logical design of any combinational and sequential digital component in this nano-electronic era and these components become a useful alternative of “CMOS” based logical components, which is already discussed in the introduction part of this paper This proposed advanced technology is a four quantum-dot based technology, where the quantum cells are placed one after another to form a quantum wire and information flow from input to output is possible over here by the interaction of neighboring quantum cells. When electrons start to flow at a clock-wise direction, it is considered as a positive polarization means binary ‘1’ and when the movement is in anti-clock wise direction the cell-polarization becomes negative means the quantum-dot cells are act as binary ‘0’
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