InP Double Heterojunction Bipolar Transistor Research Articles

A 165-Gb/s 4:1 Multiplexer in InP DHBT Technology

This paper presents a 4:1 multiplexer fabricated in InP double heterojunction bipolar transistor (DHBT) technology. The multiplexer works up to 165 Gb/s at a supply voltage of -3.2 V consuming 1.6 W. It is a half-rate multiplexer using a multi-phase clock architecture. The main design challenge was to ensure correct timing between clock and data signals

Direct Digital Synthesizer With Sine-Weighted DAC at 32-GHz Clock Frequency in InP DHBT Technology

A direct digital synthesizer (DDS) implemented in InP double heterojunction bipolar transistor (DHBT) technology is reported. This DDS uses a sine-weighted digital to analog converter (DAC) architecture that eliminates the need for a ROM. This enables operation at high frequencies with lower power consumption compared to traditional approaches. The phase accumulator is 8-bits wide and the sine-weighted DAC uses the five most significant bits (MSBs) for phase to amplitude conversion. The DDS operates up to a 32-GHz clock frequency for all frequency control words (FCWs) and can synthesize sine-wave outputs from 125 MHz to 16GHz in 125-MHz steps. The spurious free dynamic range (SFDR) is measured over the Nyquist bandwidth to be 31.00 dBc for the fundamental output frequency of 125 MHz. Over the full range of FCWs, the worst case SFDR is 21.56 dBc at an FCW of 95, and the average SFDR is 26.95 dBc. The circuit is implemented with 1891 transistors and consumes 9.45 W of power

Profiling the hot carrier induced damage in InP/InGaAs/InP double heterojunction bipolar transistors by using a current transient technique

Hot carrier induced damage in InP double heterojunction bipolar transistors (DHBTs) is investigated using a current transient technique. By monitoring the temporal evolution of base current transient, the hot carrier induced damage in the base region is quantitatively characterized. The spatial distribution of the traps at the extrinsic base surface induced by the hot carrier stress can be determined by using a charge tunneling model to model the base current transient. The results demonstrate the effectiveness of profiling the hot carrier induced damage in InP/InGaAs HBTs by the current transient technique.

Interface charge compensation in InP based heterojunction bipolar transistors with implanted subcollectors

We report InP∕In0.53Ga0.47As∕InP double heterojunction bipolar transistors (DHBTs) with implanted subcollectors. We demonstrate the compensation of charge at the regrowth interface by the use of a blanket Fe implant. An isolated N++ subcollector is then formed by a patterned Si implant. With the compensation of the interface charge, this patterned subcollector eliminates the extrinsic base-collector capacitance Ccb associated with the base interconnect pad over the entire range of bias voltages. These implanted subcollector DHBTs with the shallow Fe implant have 363GHz fτ and 410GHz fmax. The dc current gain β∼40, BVceo=4.9V, BVcbo=5.4V, and Icbo<70pA at Vcb=0.3V.

High performance InP/InAlAs/GaAsSb/InP double heterojunction bipolar transistors

DC and RF characteristics of InP/InAlAs/GaAsSb/InP double heterojunction bipolar transistors (DHBTs) are reported. The device heterostructures include InAlAs spacer layer between InP emitter and GaAsSb base layer. The impact of thin InAlAs spacer layer was investigated by comparing the DC characteristics of large-area devices fabricated on InP/InAlAs/GaAsSb/InP and conventional InP/GaAsSb/InP heterostructures. By suppressing the base tunneling current and surface recombination current, the DHBTs with thin InAlAs spacer layer exhibited 5 decade lower crossover current of 7 × 10 −11 A (collector current at unity current gain) than conventional InP/GaAsSb/InP DHBT that exhibited crossover current of 4 × 10 −6 A. The current gain also improved twice by the impact of thin InAlAs layer. To investigate the high-frequency characteristics of InP/InAlAs/GaAsSb/InP DHBTs, small-area devices employing laterally etched undercut micro-airbridges were fabricated. The unity current gain cut-off frequency, f T, of 100 GHz was obtained from a 1 × 30 μm 2 emitter DHBT.

High performance GaAsSb∕InP double heterojunction bipolar transistors grown by gas-source molecular beam epitaxy

High quality GaAsSb∕InP double heterojunction bipolar transistor (DHBT) structures were grown using gas-source molecular beam epitaxy. The substrate temperature and V/III flux ratio were optimized to grow single phase GaAsSb base layers lattice matched to InP. The dc gain as high as 40 was obtained in 60×60μm2 GaAsSb∕InP DHBTs with a 500Å carbon doped (7×1019cm−3) GaAsSb base layer. High performance DHBT with a 250Å base layer shows a current gain cutoff frequency fT of 346GHz and maximum oscillation frequency fmax of 145GHz.

Direct digital synthesizer with ROM-Less architecture at 13-GHz clock frequency in InP DHBT technology

A direct digital synthesizer (DDS) implemented in InP double heterojunction bipolar transistor (DHBT) technology is reported. The DDS has a ROM-less architecture and instead uses digital logic for phase conversion. The DDS operates up to a 13 GHz clock rate and is capable of synthesizing output frequencies up to 6.5 GHz. Measured spurious free dynamic range (SFDR)ranged from 34 dBc at low frequency control words (FCWs) to 26.67 dBc at high FCWs. The test circuit is implemented with 1646 transistors and consumes 5.42W of power

Sub-Micron INP Double Heterojunction Bipolar Transistor with Greater than 400GHZ fT and fMAX

not Available.

Neutral base recombination in InP∕GaAsSb∕InP double-heterostructure bipolar transistors: Suppression of Auger recombination in p+ GaAsSb base layers

We report on the tradeoff between current gain β and the base sheet resistance RSH in metalorganic chemical vapor deposition-grown NpN InP∕GaAs1−xSbx∕InP double-heterojunction bipolar transistors (DHBTs) with heavy base carbon-doping levels resulting in hole concentrations NB ranging from 4×1019 to 12×1019∕cm3. In contrast to Ga0.47In0.53As and GaAs–based transistors, which both display gain variations proportional to 1∕(NB×WB)2 due to Auger recombination at high doping levels, neutral base recombination in InP∕GaAsSb∕InP DHBTs is not limited by Auger processes, and the measured current gain is proportional to 1∕(NB×WB). We show that GaAs1−xSbx base layers offer a growing lifetime advantage over Ga0.47In0.53As with increasing doping levels. Potential explanations for the observed suppression of Auger recombination in the InP–GaAsSb system are proposed.

Two-dimensional DC simulation methodology for InP/GaAs0.51Sb0.49/InP heterojunction bipolar transistor

This work describes a procedure to implement a two-dimensional hydrodynamic simulation of InP/GaAs0.51Sb0.49/InP double heterojunction bipolar transistor (DHBT). It concerns the DC characteristics and allows to fit some very sensitive but still unknown or uncertain parameters of GaAs0.51Sb0.49 material, such as the band gap energy and the minority carrier lifetime. In particular, the influence of the band gap narrowing on the DHBT DC operation is analyzed. Thereafter, the mechanisms of electron–hole recombination into GaAs0.51Sb0.49 are discussed and a typical value of the electron lifetime is calculated. Finally, the drop of DHBT performances at high collector current densities is highlighted.

High-sensitivity InP/InGaAs DHBT decision circuit-design and application in optical and system experiments at 40-43 Gbit/s

A high-input-sensitivity decision D flip-flop integrated circuit was designed and fabricated in a self-aligned InP double heterojunction bipolar transistor technology (F/sub t/=180 GHz, F/sub max/=220 GHz). Circuit measurements at 40 Gbit/s show excellent eye quality, 15-mV sensitivity, and good clock phase margin. Two optical experiments, i.e., assessment of decision circuit reamplifying, reshaping, and retiming capabilities in 40-Gbit/s nonreturn-to-zero (full rate) photoreceiver and 43-Gbit/s optical signal noise ratio measurement (21.8 dB/0.1 nm for 10/sup -9/ BER) are also presented.

DC-100-GHz frequency doublers in InP DHBT technology

Broad-band monolithic integrated active frequency doublers operating in dc-100-GHz frequency range are presented. Circuits are fabricated in a self-aligned InP double heterojunction bipolar transistor process. Three integrated doubler versions have been designed. Inductive peaking and active splitting effects are quantified and compared. Circuit measurements give sinusoidal output waveform at 100 GHz with an rms timing jitter of 400 fs. Circuits have a maximum conversion gain of +1 dB at 60 GHz. the fundamental suppression is better than 24 dB in the whole frequency range.

4-bit adder-accumulator at 41-GHz clock frequency in InP DHBT technology

A 41-GHz 4-b adder-accumulator test circuit implemented in InP double heterojunction bipolar transistor (DHBT) technology using 624 transistors is reported. High clock rates are obtained by combining the logic functions into pipelined latches. The adder-accumulator contains a single-level parallel-gated carry circuit that is used as a step toward reduced power consumption. The carry circuit has a maximum clock frequency of 55 GHz. The accumulator architecture employs modular, pipelined 2-b adders and is cascadable to 2 N-bits. The test circuit includes a 4-b digital to analog converter (DAC) that facilitates demonstration of high-speed operation.

Direct extraction of InP HBT noise parameters based on noise-figure measurement system

A new method for the determination of the four noise parameters of an InP double heterojunction bipolar transistor (DHBT) based on a 50-/spl Omega/ noise measurement system without a microwave tuner is presented. The noise parameters are determined based on the noise correlation matrix technique by fitting the measured noise figure of the active device. On-wafer experimental verification up to 20 GHz is presented and a comparison with a tuner based method is given. Good agreement is obtained between measured and calculated results up to 20 GHz for the InP/InGaAs DHBT with a 1.6/spl times/20 /spl mu/m/sup 2/ emitter over a wide range of bias points.

Microwave noise modeling for InP-InGaAs HBTs

Analytical expressions for the noise parameters of microwave InP double heterojunction bipolar transistors (DHBTs) are presented in this paper. These expressions are derived from an accurate small-signal and noise equivalent-circuit model, which takes into account the influences of the base-collector capacitance and the base resistance distributed nature. Pad capacitances and series inductances are also included. Further simplified expressions for noise parameters in the low-frequency range are given. Good agreement is obtained between measured and calculated results up to 20 GHz for InP-InGaAs DHBTs with a 5/spl times/5 /spl mu/m/sup 2/ emitter area over a wide range of bias points.

0.1–42 GHz InP DHBT distributed amplifiers with 35 dB gain and 15 dBm output

An InP double hetero-junction bipolar transistor (DHBT) distributed power amplifier MMIC with 35 dB gain, 42 GHz bandwidth and 15 dBm output power is reported. This represents the highest power and largest gain reported over this bandwidth from a single chip HBT amplifier. A lumped preamplifier with a novel distributed output is used to obtain high gain and wide bandwidth at these power levels.

Thermal properties of metamorphic buffer materials for growth of inp double heterojunction bipolar transistors on gaas substrates

Metamorphic double heterojunction bipolar transistors (MDHBT) using InP or InAlP as metamorphic buffer layers were grown on GaAs substrates. For devices using InP buffer layers on GaAs substrates, measured junction-ambient temperature rise at 7.5 mW power dissipation is comparable to those of devices grown on InP substrates, while much larger temperature rises are observed when InAlP buffer layers are employed. By comparing the measured temperature rise with that computed as a function of the known transistor geometry and unknown buffer-layer thermal conductivity, we estimate that the thermal conductivity of a uniform InP buffer layer is 35/spl plusmn/5 W/k-m, while a linearly graded InAlP buffer layer with 0.2 /spl mu/m InP upper layer has 8/spl plusmn/3 W/k-m effective thermal conductivity. These results strongly suggest the use of InP metamorphic buffer layers in metamorphic InP-based DHBTs grown on GaAs substrates.

Ultrahigh-speed direct digital synthesizer using InP DHBT technology

Direct digital synthesizers (DDS) offer advantages such as precise beam shaping and forming over conventional RF approaches. This paper discusses novel design and process techniques that enable direct digital synthesis of S-band output frequencies using our current InP double-heterojunction bipolar transistor technology with a cantilevered base layer and undercut collector. The DDS chip operates at the world record clock rate of 9.2 GHz and capable of generating sinewaves up to 4.56 GHz. It also demonstrates state-of-the-art phase noise of -140 dBc at a frequency offset of 1 kHz and a clock frequency of 2.5 GHz. Further design and process improvements will be implemented in future generation circuits that will enable synthesis of Ku-band frequencies.

Mux-driver-EAM in single module – a solution for ultra-high bit rate applications

The integration of the final three higher-speed functions of an electro-optical emitter in a single module – the multiplexer, the driver and the electroabsorption modulator (EAM) – is demonstrated. The module has operated up to a bit rate of 40 Gbit/s. The Mux-driver was made using in-house InP-double heterojunction bipolar transistor technology. The proposed solution has the following features: compactness, low bit rate inputs, no need of a bandpass capacitor or bias tee between driver and EAM, and possibility to adjust the driving offset voltage, electrical control output, low power consumption, etc.

Scaling of microwave noise and small-signal parameters of InP/InGaAs DHBT with high DC current gain

The scaling of noise and small-signal parameters of InP double heterojunction bipolar transistors (DHBTs) with high DC gain are presented for the first time in this brief. As InP DHBTs have very low surface recombination and high DC current gain, the large size device can be viewed as consisting of n identical subcells. Using this approach, a set of equations was derived, which relate the noise and small-signal parameters between the large-size device and the subcells for scaling purposes. The experimental and theoretical results show that at the same collector current density and collector-emitter voltage, good scaling of the noise and small-signal parameters can be achieved between the large-size device and the subcells. Because of the nonscalable external base-collector capacitor (C/sub bc/), the effects of C/sub bc/ on the noise and small-signal parameters are also investigated. The large base-collector capacitance acts as a negative feedback providing the lower minimum noise figure value and higher value of the imaginary part of the optimum source admittance. The good agreement between the measured and the calculated results supports the scaling approach developed in this work for InP DHBTs that may be useful for the design of high frequency circuits using InP-based HBTs.