Injection-locked Frequency Divider Research Articles

A 40.3–50.5 GHz locking range transformer‐based injection‐locked frequency divider utilizing a high third harmonic rejection buffer

AbstractInjection‐locked dividers feature ultrahigh operating frequency, low power consumption, and low phase noise, making them suitable for Q‐band phase‐locked loop. This paper presents a transformer‐based divide‐by‐4 injection locking frequency divider with a high third harmonic rejection buffer based on 40‐nm CMOS technology. Employing a fourth‐order transformer resonator enhances the third‐order harmonic amplitude, increasing the injection efficiency and expanding the locking range. The proposed high third harmonic rejection buffer using a source degeneration inductor can effectively suppress the output of the third harmonic caused by the resonator, ultimately yielding a clean fundamental frequency signal. Simulation results demonstrate that the proposed divide‐by‐4 injection‐locked frequency divider (ILFD) achieves a locking range of 10.2 GHz (from 40.3 to 50.5 GHz) with 0 dBm input signal. The core divide‐by‐4 ILFD circuit consumes 4.6 mW power with a 0.9 V supply and occupies an area of 0.026 mm2.

A wide locking range injection‐locked frequency divider with an auto‐adjusted injection bias

AbstractThis paper presents a Ku‐band divide‐by‐2 direct injection‐locked frequency divider (ILFD) with a wide locking range (LR) and high input sensitivity. The proposed ILFD incorporates an auto‐adjusted injection bias that uses a power detector (PD) to convert the power of the injected signal to a DC voltage. The bias voltage of the injection transistor is then auto‐adjusted in response to the output of the PD. The proposed ILFD employs a 2‐bit switched capacitor array to further enhance the entire LR. Implemented in a 65‐nm CMOS process, the experimental results show that the proposed ILFD achieves an LR of 62.3% (10.5–20 GHz) and 51.2% (11.2–18.9 GHz) at 0 and −10 dBm injection power, respectively. The proposed ILFD consumes 3.6 mW from a 0.6 V supply, and the core area is 0.067 mm2.

Design and Analysis of Divide-by-4 Injection-Locked Frequency Divider Using Gain-Boosting Injection Balun and Dual Linear Mixer Techniques

Design and Analysis of Divide-by-4 Injection-Locked Frequency Divider Using Gain-Boosting Injection Balun and Dual Linear Mixer Techniques

A 58-%-Lock-Range Divide-by-9 Injection-Locked Frequency Divider Using Harmonic-Control Technique

This paper presents a divide-by-9 injection-locked frequency divider (ILFD). It can lock onto about 6-GHz input with a locking range of 3.23 GHz (58%). The basic concept of the ILFD is based on employing self-gated multiple inputs into the multiple-stage ring oscillator. A wide lock range is also realized by adapting harmonic-control circuits, which can boost specific harmonics generated by mixing. The ILFD was fabricated using a 55-nm deeply depleted channel (DDC) CMOS process. It occupies an area of 0.0210mm2, and consumes a power of 14.4mW.

A Q-Band CMOS Image-Rejection Receiver Integrated with LO and Frequency Dividers

This paper presents a Q-band image-rejection receiver using a 65 nm CMOS technology. For a high image-rejection ratio (IMRR), the Q-band receiver employs the Hartley architecture which consists of a Q-band low-noise amplifier, two down-conversion mixers, a 90° hybrid coupler, and two IF baluns. In addition, a Q-band fundamental voltage-controlled oscillator (VCO) and a frequency divider chain divided by 256 are integrated into the receiver for LO. A charge injection technique is employed in the mixers to reduce the DC power while maintaining a high conversion gain and linearity. The VCO adopts a cross-coupled topology to secure stable oscillation with high output power in the Q-band. The frequency divider chain is composed of an injection-locked frequency divider (ILFD) and a multi-stage current-mode logic (CML) divider to achieve a high division ratio of 256, which facilitates the LO signal locking to an external phase-locked loop. An inductive peaking is employed in the ILFD to widen the locking range. The Q-band image-rejection receiver exhibits a peak conversion gain of 16.4 dB at 43 GHz. The IMRR is no less than 35.6 dBc at the IF frequencies from 1.5 to 5 GHz.

A 24.4~39.6 GHz Wide Locking Range Divide-by-4 Injection-Locked Frequency Divider With High Harmonic Rejection Ratio

In this brief, an innovative divide-by-4 injectionlocked frequency divider (ILFD) is hereby proposed to expand the locking range (LR) and improve the harmonic rejection ratio (HRR). Specifically, a fourth-order transformer-based resonator is adopted to improve the LR without any additional tuning capacitors, and a dual-tank network is proposed to optimize the harmonic rejection. To implement the proposed techniques, two chips with different networks are analyzed, designed, and fabricated in a 28-nm CMOS technology. The chip with the dualtank network is proven to achieve the bandwidth from 24.4 to 39.6 GHz, i.e., 47.5% with the second and third harmonic rejection ratios of better than 32 dBc and 11 dBc, while the other chip achieves the bandwidth from 30.8 to 42.6 GHz, i.e., 32.2%. Additionally, the ILFD with the dual-tank network is confirmed to possess differential output power from -17.5 to -19.8 dBm, consuming only 7.4 mW dc power under a 0.5-V supply.

Current‐reused CMOS 8:1 injection‐locked frequency divider employing two wide locking range subfrequency dividers

AbstractConventional current‐reused 8:1 injection‐locked frequency dividers (ILFDs) either use a 2:1 p‐core LC sub‐ILFD stacking on a direct‐injection 4:1 n‐core LC sub‐ILFD or a 2:1 ring‐oscillator LC sub‐ILFD stacking on a direct‐injection 4:1 n‐core LC sub‐ILFD. Because the current‐mode 4:1 n‐core LC sub‐ILFD normally has a smaller locking range, it restricts the locking range of a current‐reused 8:1 ILFD. This article studies a wide locking range 8:1 current‐reused ILFD designed in a 0.18 μm CMOS process. The designed 8:1 ILFD uses a 4:1 ring‐oscillator LC sub‐ILFD stacking on a direct‐injection 2:1 n‐core LC sub‐ILFD. At the core power consumption 19.53 mW and at the incident power of 0 dBm, the 8:1 locking range is 1.11 GHz (65.37%), from the incident frequency 4.16–8.2 GHz.

Using tail current phase shift technique to improve locking range injection‐locked frequency divider

SummaryIn this article, an injection‐locked frequency divider (ILFD) is presented. By assuming the maximum phase of the tank current, we obtain a relation for the lock range. Besides, the effects of parasitic capacitors on the lock range have been probed. The analysis shows that the greater the phase difference between the tail current and injected signal, the phase of the tank current increases and, consequently, the lock range also increases. The accomplished simulations confirm the correct performance of the proposed design and the extracted relationships. The simulations have been CMOS technology and with a 0.9‐V supply voltage. The results show that the current consumption equals 3.7 mA and the power consumption equals 3.33 mW. The proposed ILFD lock range with phase shift technique with power input signal 0 dBm is equal to 5.1 GHz (3.6–8.7 GHz), and the relative percentage of the lock range is also 83%.

Analysis and Design of Tuning-Less mm-Wave Injection-Locked Frequency Dividers With Wide Locking Range Using 8th-Order Transformer-Based Resonator in 40 nm CMOS

Three tuning-less ultra-wide locking range (LR) transformer-based millimeter-wave (mm-wave) injection-locked frequency dividers (ILFDs) are presented. An eighth-order transformer-based resonator is proposed to improve the LR without an extra tuning mechanism or chip area. The operation principle of high-order transformer-based resonator in ILFDs based on the impedance diagram is analyzed. By comparing different high-order transformer-based resonators, the proposed resonator is the best option for the ultra-wide LR ILFD design. Also, the design considerations and tradeoffs of the implemented resonator are discussed. Furthermore, an inductive gain peaking technique is adopted to ensure start-up conditions and achieve low power consumption. Three ILFDs are designed and fabricated in 40-nm CMOS technology. The first chip exhibits a best-in-class LR of 104.5% from 28.8 to 91.9 GHz while consuming 5.8 mW with a 0.9-V power supply. The second chip achieves the best figure of merit (FoM) up to 26.6 GHz/mW and 79.6% from 31- to 72-GHz LR with a 0.5-V power supply. The third chip obtains an LR of 108.9% from 20 to 67.8 GHz while consuming 4.9 mW with a 0.9-V power supply. Furthermore, 6-dB phase noise differences of the three chips are achieved, which is close to the theoretical value.

Injection-Locking Techniques for CMOS Millimeter-Wave and Terahertz Signal Generation

This brief presents a comprehensive tutorial on the recent advances of injection-locking techniques used for millimeter-wave (mm-Wave) and terahertz (THz) signal generation systems. Injection locking has the potential to significantly improve the system performance in terms of low phase noise and low power consumption. The focus will be on the state-of-the-art injection-locking techniques to effectively widen the locking range and reduce the phase noise, including injection-locked frequency dividers (ILFDs), injection-locked frequency multipliers (ILFMs), and sub-harmonic injection-locked phase-locked loops (IL-PLLs).

Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology

Based on a detailed analysis of harmonic generation in ring-based injection-locked frequency dividers (ILFDs), this article shows that concurrent injection signals can be generated in these stages by driving both tail and direct injectors with the same input signal. Based on this result, a novel ring-based divide-by-five ILFD is presented, where multi-injection is reinforced by a dual-path scheme, largely broadening the locking range with no penalty in power dissipation. The stage, implemented in a 28-nm CMOS process, operates over the 8-to-101.6-GHz frequency range achieving a >20% locking over the 13.6–69.1-GHz interval, with 5.6-mW maximum power consumption from a 0.9-V supply. The stage also achieves 101.6 GHz, the highest operating frequency among state-of-the-art CMOS ILFDs by five, with 2.6% locking range.

An ultra-wideband injection-locked frequency divider with a multi-order resonator and the passive injection-boosted technique

This paper presents an ultra-wideband injection-locked frequency divider (ILFD) design which is applicable to a multi-applications system. A transformer-based multi-order resonator is utilized in the ILFD to attain a flat phase response. The passive injection-boosted technique is proposed to increase the injection signal amplitude and thus widen the locking range. With the injection-boosted technique and the multi-order resonator, the proposed ILFD demonstrates a measured locking range of 50GHz, covering 48GHz to 98GHz. The divider designed in a 40-nm process consumes a DC power of 11.2mW excluding buffers and occupies a core size of 0.38×0.63mm2.

A Wide-Band Divide-by-2 Injection-Locked Frequency Divider Based on Distributed Dual-Resonance Tank

A wide-band divide-by-2 injection-locked frequency divider (ILFD) based on a distributed dual-resonance high-order tank is presented. The ILFD employs a distributed LC network as the dual resonance tank and achieves an ultra-wide locking range. Fabricated in a 65 nm 1P7M LP-CMOS process, the divide-by-2 ILFD consumes 7 mW from a 0.7 V power supply and realizes a locking range of 87.0%, from 13 GHz to 33 GHz. The core circuit occupies an area of 0.22 mm × 0.5 mm.

A Divide-by-Three ILFD With Second Harmonic Enhancement

This letter presents a low-voltage divide-by-three injection-locked frequency divider (ILFD) with a second harmonic enhancement technique. The injection current generated from the extra divide-by-two injection path is enhanced compared with the former work, thus the larger locking range (LR). Fabricated in the CMOS 65-nm technology, the core circuit consumes 5.18 mW from a 0.6-V power supply. Under 0 dBm signal injection, the measured largest LR achieves 19.03% ranging from 23.30 to 28.20 GHz without frequency tuning. By using a varactor, the bandwidth can range from 23.30 to 31.02 GHz, which can be used as the first stage frequency division in the phase-locked loop (PLL) of the 5G transceiver.

A design technology of a wideband mm-wave injection-locked frequency divider

A design technology of the wideband mm-wave injection-locked frequency divider (ILFD) is proposed and based on the 40-nm CMOS technology, a relating chip is designed for verification. In order to solve the problem of the narrow locking range (LR) in conventional mm-wave ILFDs, the transformer-based high-order resonator is utilized to generate the rippled phase response, enlarging the LR efficiently; Additionally, for the propose of reducing the equivalent parasitic capacitance from the gate of differential pairs in mm-wave band, an inductive divider feedback technology is proposed, realizing the boost of oscillation frequency. Besides, the injection-locked conditions of phase and gain for a modified model are theoretically deduced and the enhancement of oscillation frequency is analyzed and verified by simulations. The layout is drawn and the parasitic parameters are extracted to acquire the post-simulation results which suggest a LR of 36.9% from 52.6~76.4 GHz under 0.8 V power supply while a LR of 45.1% from 50~79.1 GHz, consuming 2.9 mW achieving an FoM of 10.0 GHz/mW under 0.62 V supply voltage.

A 19–48.3-GHz 6th-Order Transformer-Based Injection-Locked Frequency Divider With 87.1% Locking Range in 40-nm CMOS

This brief presents a 19-48.3-GHz fully-on-chip divided-by-2 injection-locked frequency divider (ILFD) based on a 6 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> -order transformer for a wide locking range in 40-nm CMOS technology. The proposed 6 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> -order transformer extends the resonator's locking range by introducing more zeros and poles that could widen the frequency range satisfying the locking conditions. Furthermore, an inductive gain peaking technique is adopted to ensure start-up conditions and achieve low power consumption. The measurement results demonstrate a locking range of 29.3 GHz from 19 GHz to 48.3 GHz, which satisfies most applications for different nations' 5G standards. The chip occupies a core area of 0.0518 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and dissipates 2.88 mW from a 0.6-V voltage supply.

Low‐power divide‐by‐4 injection‐locked frequency divider using an inductive resonating technique

AbstractAn injection‐locked frequency divider (ILFD) with the low‐power divide‐by‐4 feature for K‐band applications in a 0.18 μm CMOS process is reported in this letter. Output differential signals (f0 = 4f0‐3f0) are obtained by the third‐harmonic signals (3f0) from the free‐running core mixing with injection signals (4f0) through injection transistors in the proposed ILFD. This improves the locking range and saves power consumption by employing an inductive resonator technique and double cross‐coupled transistor pairs without the help of varactors. For the proposed ILFD, the measured free‐running frequency is 5.126 GHz and input injection frequencies at an input power level of 0 dBm are from 19.4 to 21.4 GHz. From a supply voltage of 1.5 V, the proposed ILFD core only dissipates 4.2 mW.

English

In this paper, we introduce an approach to increase density of field-effect transistors framework a injection-locked frequency divider. Framework the approach, we consider manufacturing the inverter in heterostructure with specific configuration. Several required areas of the heterostructure should be doped by diffusion or ion implantation. After that dopant and radiation defects should by annealed framework optimized scheme. We also consider an approach to decrease value of mismatch-induced stress in the considered heterostructure. We introduce an analytical approach to analyze mass and heat transport in heterostructures during manufacturing of integrated circuits with account mismatch-induced stress.

An Approach to Decrease Dimensions of Field-Effect Hetero-Transistors in an Injection-Locked Frequency Divider with Account Miss Match Induced Stress and Porosity of Materials to Increase Their Density

In this paper we introduce an approach to increase density of field-effect transistors framework an injection-locked frequency divider. Framework the approach we consider manufacturing the inverter in heterostructure with specific configuration. Several required areas of the heterostructure should be doped by diffusion or ion implantation. After that dopant and radiation defects should by annealed framework optimized scheme. We also consider an approach to decrease value of mismatch-induced stress in the considered heterostructure. We introduce an analytical approach to analyze mass and heat transport in heterostructures during manufacturing of integrated circuits with account mismatch-induced stress.

An 18.8-33.9 GHz, 2.26 mW Current-Reuse Injection-Locked Frequency Divider for Radar Sensor Applications.

An 18.8–33.9 GHz, 2.26 mW current-reuse (CR) injection-locked frequency divider (ILFD) for radar sensor applications is presented in this paper. A fourth-order resonator is designed using a transformer with a distributed inductor for wideband operating of the ILFD. The CR core is employed to reduce the power consumption compared to conventional cross-coupled pair ILFDs. The targeted input center frequency is 24 GHz for radar application. The self-oscillated frequency of the proposed CR-ILFD is 14.08 GHz. The input frequency locking range is from 18.8 to 33.8 GHz (57%) at an injection power of 0 dBm without a capacitor bank or varactors. The proposed CR-ILFD consumes 2.26 mW of power from a 1 V supply voltage. The entire die size is 0.75 mm × 0.45 mm. This CR-ILFD is implemented in a 65 nm complementary metal-oxide semiconductor (CMOS) technology.