Injection-locked Frequency Divider Research Articles

A Fractional-N Counter-Assisted DPLL With Parallel Sampling ILFD

A fractional-N digital phase-locked loop (DPLL) with ring oscillator based injection-locked frequency divider (ILFD) and parallel sampling phase samplers is presented. The ILFD utilizes dual path injection technique to achieve wide locking range (4.2–23 GHz) and low power consumption. A low-power parallel sampling phase sampler based time-to-digital converter (TDC), which achieves sub-gate-delay resolution by sampling the ILFD’s multi-phase outputs using parallel sampling technique, is proposed. The TDC resolution is determined by delay spacing between successive sampling clocks, which is ensured through digital calibration loops. Due to injection locking, no calibration is required to normalize the TDC step to the DCO output period. A hybrid high speed counter architecture, combining a 2 bit asynchronous counter and a 6 bit synchronous counter, is proposed to achieve high speed (>4 GHz) operation with low power consumption. The proposed design is fabricated in a 65 nm CMOS process and occupies 0.1 mm2. The synthesizer covers 13.6–16.8 GHz output and dissipates 8.5 mW. The measured output phase noise achieves −89 dBc/Hz and −125 dBc/Hz at 100 kHz and 10 MHz offsets, respectively. The measured jitter is less than 0.43 ps.

A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad

This paper presents a low-power low-noise 60 GHz frequency synthesizer using a 20 GHz subsampling phase-locked loop (SS-PLL) and a 60 GHz tail-coupling quadrature injection-locked oscillator (QILO) which results in a lower in-band phase noise and out-of-band phase noise, respectively. To save battery life, dual-step-mixing injection-locked frequency divider (ILFD) enhances locking range for high division ratio. Moreover, tail cross-coupling technique in a QILO helps boost negative transconductance $({{-g}}_{m})$ of the 60 GHz QILO which allows the use of larger inductance for power reduction. Implemented in 65 nm CMOS, it can cover required channels from 58.32 to 64.80 GHz with quadrature outputs. It consumes 24.2 and 7.8 mW from 20 GHz SS-PLL and QILO, respectively. The proposed synthesizer achieves $-78.5\; \text{dBc/Hz}$ at 100 kHz offset, $-122\text{dBc/Hz}$ at 10 MHz offset, and a figure-of-merit (FoM) of $-236\text{dB}$ .

Review: capacitive cross-coupled injection-locked frequency dividers

This paper reviews the use of capacitive cross-coupled oscillator in the design of wide locking-range injection-locked frequency dividers (ILFDs). The advantages of capacitive cross-coupled ILFDs as compared to direct cross-coupled ILFDs are lower power consumption and wider locking range. Experimental examples of CMOS divide-by-2, divide-by-3 and divide-by-4 ILFDs are used to demonstrate the RF performance improvement by using this circuit topology.

Divide‐by‐2 LC injection‐locked frequency divider with wide locking range at low and high injection powers

SummaryA wide locking range nMOS divide‐by‐2 RLC injection‐locked frequency divider (ILFD) was designed and implemented in the TSMC 0.18‐µm BiCMOS process. The ILFD is based on a cross‐coupled oscillator with one direct injection MOSFET and a RLC resonator. The RLC resonator is used to extend the locking range so that dual‐band locking ranges can be merged in one locking range at both low and high injection powers. At the drain‐source bias of 0.9 V for switching transistors, and at the incident power of 0 dBm the locking range of the divide‐by‐2 ILFD is 7.24 GHz, from the incident frequency 2.65 to 9.89 GHz, the locking range percentage is 115.47%. The power consumption of ILFD core is 8.685 mW. The die area is 0.726 × 0.930 mm2. Copyright © 2016 John Wiley & Sons, Ltd.

Triple‐resonance RLC‐tank divide‐by‐2 injection‐locked frequency divider

Conventional CMOS injection-locked frequency dividers (ILFDs) were often designed with a single-resonance LC resonator and they have a single-band locking range. Wide-locking range in these ILFDs was obtained at the cost of lower output power. A triple-resonance (TR) resistor (R), inductor (L) and capacitor (C)-tank ILFD is presented to design a wide-locking range CMOS divide-by-2 circuit, which is based on a cross-coupled n-core MOS pair. The TR ILFD has three overlapped locking ranges seen as one-band locking range at high microwave injection power and it has large output power. At the core power consumption of 6.76 mW and at the microwave input power of 0 dBm, the divide-by-2 TR ILFD achieve a maximum locking range of 5.77 GHz (105.2%) from 2.6 to 8.37 GHz.

Low-power CMOS injection-locked and current-mode logic frequency dividers in a 50 GHz LC cross-coupled oscillator

This paper aims to design a low-power and high-frequency divider in an integrated CMOS phase-locked loop. The proposed frequency divider is a two-step divider composed of an injection-locked frequency divider (ILFD) and a current-mode logic (CML) frequency divider. The ILFD has a structure similar to an LC cross-coupled oscillator to adjust the frequency alignment between the oscillator and the ILFD. The LC cross-coupled oscillator operates at 50 GHz, and the ILFD is supposed to provide a divide-by-2 (/2) operation. The CML frequency divider, which is used as the second-stage divider, is applied with an inductive peaking structure for a wide band with low power consumption. The proposed two-step frequency divider is designed with a 0.18 µm CMOS process. By varying the numbers of the ILFD and the CML divider, the characteristics of power consumption are also studied. Post-layout simulation shows that the /2 ILFD and the /128 CML frequency divider operate at an input frequency of 50 GHz, with power consumption of 37.8 mW, and results indicate a low-power two-step divider at high frequency.

CMOS injection‐locked frequency divider with division factor of three

A divide-by-3 injection locked frequency divider is presented. The divider works based on a two-stage differential ring oscillator in which two quadrature signals are used as injection signals. The analytical relationship for the divider locking range is derived and the main factors impacting on this parameter are discussed. The circuit has been designed in a 0.18 μm CMOS technology with a supply voltage of 1.8 V. Post layout simulation on the divider including all layout wiring parasitic elements such as resistance, capacitance and inductance shows that the typical locking range of the divider is over 3 GHz from 1 to 4.2 GHz for −0.5 dBm injection signal level while its total power dissipation for 4.2 GHz input injection signal is 505 μW at the supply of 1.8 V.

A Wide Locking Range and Low Power Divide-by-2/3 LC Injection-Locked Frequency Divider

A direct divide-by-2/3 LC injection-locked frequency divider (ILFD) is presented in this paper. The proposed ILFD circuit is based on a CMOS LC tank oscillator coupled with an injection NMOS transistor in series with an inductor. Together with body-biased technique and current-reused topology, the locking range of the ILFD is improved and the power consumption is reduced. The circuit is implemented in a 0.18[Formula: see text][Formula: see text]m standard RF CMOS process. At the incident power of 0[Formula: see text]dBm, the measured locking range of the divide-by-2 and divide-by-3 modes are from 5.37[Formula: see text]GHz to 7.68 (8.07[Formula: see text]GHz to 11.4[Formula: see text]GHz) GHz, and the core circuit without buffers consumes 3[Formula: see text]mW at the supply voltage of 1.5[Formula: see text]V. The chip only occupies [Formula: see text] without the pads and the buffers.

Enhanced locking range technique for frequency divider using dual‐resonance RLC resonator

An enhanced locking range technique for a CMOS injection-locked frequency divider (ILFD) is presented, which uses a cross-coupled oscillator with a dual-resonance RLC resonator. This ILFD has dual locking ranges at a fixed bias, and the resistor in the resonator is used to have overlapping dual locking ranges so that a single-band wide-locking range is obtained. At the incident power of 0 dBm, the locking range of the divide-by-2 ILFD is 6.7 GHz, from 3 to 9.7 GHz, and the locking range percentage is 105.51%.

A V-Band CMOS Divide-by-Three ILFD With Frequency-Dependent Injection Enhancement

This letter presents a V-band divide-by-three injection-locked frequency divider (ILFD) with low power consumption and wide locking range, by using the novel frequency-dependent injection enhancement (FDIE) technique. The optimum tradeoff between amplitude and phase locking conditions of the FDIE circuit is first analyzed theoretically. Then a current-reused differential pre-amplifier loaded with a moderate-k transformer for FDIE circuit is proposed to obtain the greatest locking range under such trade-off. Fabricated in a 65 nm CMOS technology, the proposed ILFD prototype demonstrates a wide input locking range of 54.5-62.36 GHz (13.5%) and only 2.5 mA current consumption with 1.2 V supply.

Divide-by-4 capacitive cross-coupled injection-locked frequency dividers

Wide locking range is an important parameter for injection-locked frequency divider (ILFD) to cope with the supply voltage variation. This paper proposes a wide locking range divide-by-4 ILFD implemented in the TSMC 0.18 μm 1P6 M CMOS process. The ILFD uses a capacitive cross-coupled voltage-controlled oscillator as the core. The dc gate bias of cross-coupled FETs is smaller than dc drain bias to optimize the power and locking range. Dual-resonance LC resonator is also used to enhance the locking range. At the drain-source bias of 1.2 V, and at the incident power of 0 dBm the measured locking range of divide-by-4 ILFD is 3.3 GHz, from the incident frequency 7.5---10.8 GHz, the percentage is 36.06%. The core power consumption is 11.83 mW. The die area is 0.883 ? 0.851 mm2.

A triple-band divide-by-2 CMOS injection-locked frequency divider

A triple-band and wide operation range divide-by-2 injection-locked frequency divider (ILFD) using a TSMC 0.18 μm 1P6 M CMOS technology is presented. The ÷2 ILFD circuit is realized with a cross-coupled n-core MOS LC-tank oscillator with a 6th order LC resonator constructed from three single-resonance parallel LC resonators. The core power consumption of the ILFD core is 11.6 mW at the supply voltage of 1 V. The free-running ILFD can operate at three frequency bands: 8.75, 5.79 and 3.7 GHz, and the ILFD operation range covers a high-band frequency range from 17.1 to 18.3 GHz, a middle-band from 10.1 to 12.7 GHz, and a low-band from 6.0 to 7.7 GHz. The band selection is obtained by tuning the varactor's control bias.

Wide‐locking range single‐injection divide‐by‐3 injection‐locked frequency divider

ABSTRACTThis letter presents a wide‐locking range CMOS divide‐by‐3 injection‐locked frequency dividers (ILFD) using single‐ended injection signal. The fabricated 0.18 μm CMOS ÷3 ILFD uses cross‐coupled switching transistors, single‐injection MOSFET, and a dual‐resonance RLC resonator. The consumed power of the ÷3 ILFD core is 7.97 mW at the DC drain‐source voltage 0.76 V. At an external injected signal power Pinj = 0 dBm, the measured locking range is 2.97 GHz (25.25%) from 10.28 to 13.25 GHz and the operation range is 5.17 GHz (48.5%) from 8.08 to 13.25 GHz. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:2720–2723, 2015

Designs of K-Band Divide-by-2 and Divide-by-3 Injection-Locked Frequency Divider With Darlington Topology

This paper presents divide-by-2 and divide-by-3 injection-locked frequency dividers (ILFDs) using a Darlington cell in a TSMC 0.18- $\mu$ m CMOS process. The Darlington cell has higher transconductance than the traditional cross-coupled common source cell for free-running oscillator that reduces the power consumption of ILFDs. Besides, an LC resonance technique is used in the proposed divide-by-2 ILFD to achieve lower power consumption and wide locking range. This work provides an analytic method to choose the injector size for widening the locking range and lowering the power consumption. The measured locking range of the proposed divide-by-2 ILFD is from 20.5 to 22.9 GHz. The measured operation range of the divide-by-3 ILFD is from 24.71 to 28 GHz. The measured phase noises of two dividers under locked condition are ${-}{\hbox{138.3}}$ and ${-}140.35$ dBc/Hz at an offset of 1 MHz when the input referred signals have phase noises of ${-}{\hbox{132.54}}$ and ${-}{\hbox{131.5}}$ dBc/Hz, respectively. Meanwhile, both phase noise differences with respect to injection signal are 5.76 and 8.85 dBc, which are close to the theoretical values of 6 and 9.5 dBc. The core power consumptions are 1.73 and 5.13 mW with the supply voltages of 1.2 and 1.45 V, and the chip sizes are 0.8 $\,\times\,$ 0.75 mm $^{2}$ and 0.77 $\,\times\,$ 0.79 mm $^2$ , respectively.

Divide-by-3 injection-locked frequency dividers using dual-resonance resonator

This paper exploits the application of dual-resonance LC resonator in the design of wide-locking-range injection-locked frequency dividers (ILFDs). The tail-injection and direct-injection divide-by-3 ILFD circuits in a standard CMOS process are realized with a pair of cross-coupled nMOSFETs with a dual-resonance LC-resonator. The locking range enhancement techniques such as linear mixer and quality-factor degradation are used to design wide-locking range divide-by-3 ILFD. At the incident power of 0 dBm the locking range of the divide-by-3 ILFD is 4.6 GHz (43.3 %), from the incident frequency 8.3 to 12.9 GHz.

Wide‐locking range divide‐by‐4 injection‐locked frequency divider using injection MOSFET DC‐biased above threshold region

SummaryA novel wide locking range divide‐by‐4 injection‐locked frequency divider (ILFD) is proposed in the paper and was implemented in the TSMC 0.18 µm 1P6M CMOS process. The divide‐by‐4 ILFD uses two injection transistors in series and DC‐biased above threshold voltage and a frequency doubler to enhance the function of linear mixers. At the drain‐source bias of 0.9 V and at the incident power of 0 dBm, the locking range of the divide‐by‐4 is 2.6 GHz; from the incident frequency 12.2 to 14.8 GHz, the percentage is 19.26%. The core power consumption is 10.35 mW. The die area of ILFD is 1.026 × 0.943 mm2. Copyright © 2015 John Wiley & Sons, Ltd.

Wide-locking range LC-tank divide-by-4 injection-locked frequency divider using transformer feedback

A wide locking range, injection locked frequency divider (ILFD) circuit topology is explored. The modulus-four ILFD utilizes a cross-coupled voltage-controlled oscillator in conjunction with transformer feedback, parallel-tuned resonator, and two-segment, series mixers at the injection point. The transformer feedback and two-segment mixing circuit topology achieves a locking range of 2.7 GHz (14.1 to 16.8 GHz) at an injection point bias of 0.9 Vdc and 0 dBm injection power. Spectral measurements at the ILFD output demonstrate proper phase-lock operation and expected phase noise reduction using a high quality signal source at the ILFD input. The ILFD is implemented in the TSMC 0.18 μm 1P6M CMOS process, utilizes a die area of 0.839 × 0.566 mm2 and consumes 16.56 mW. © 2015 Wiley Periodicals, Inc. Int J RF and Microwave CAE 25:557–562, 2015.

Injection-locked frequency divider using single-injected dual-injection MOSFETs

A wide locking range and operation range push–push divide-by-4 injection-locked frequency divider (ILFD) is proposed in the paper and was implemented in the TSMC 0.18μm BiCMOS process. The divide-by-4 ILFD uses a cross-coupled voltage-controlled oscillator (VCO) with a parallel-tuned LC resonator for easy startup oscillation and single-ended injected dual-injection transistors. The common drain node of dual injection transistors is AC-tied to the output of a frequency doubler. At the drain-source bias of 0.8V, and at the incident power of 0dBm the operation range of the divide-by-4 is 3.23GHz, from the incident frequency 15.85 to 19.08GHz, the percentage is 18.49%. The locking range of the divide-by-4 is 1.4GHz, from the incident frequency from 17.08GHz to 19.08GHz, the percentage is 11.06%. The core power consumption is 6.53mW. The die area is 0.83×0.597mm2.

Modified Inductive Peaking Direct Injection ILFD With Multi-Coupled Coils

In this letter, we present the design of a fully differential direct injection locked frequency divider (D-ILFD) in 65 nm CMOS process. Based on strong coupling of multi-coupled coils, we propose a modified inductive peaking in the D-ILFD to improve the locking range with a compact core area. The proposed injection locked frequency divide-by-2 divider demonstrates an operation frequency range of 6.7 GHz for a low injected power of -8 dBm and single-ended output power of -4 dBm. With a supply voltage of 1 V, the power consumption of the D-ILFD is 2.5 mW and the power efficiency (Pout/PDC) is 8.3%.

Ring Oscillator Based Injection Locked Frequency Divider Using Dual Injection Paths

Ring oscillator based injection locked frequency dividers (ILFD) generally feature higher power efficiency compared to conventional static frequency dividers. However it is difficult for ring oscillator based ILFDs to achieve large division ratio and wide input locking range at the same time. To increase the input locking range, a ring oscillator based ILFD utilizing dual injection technique is proposed in this letter. For this, both tail injection and direct injection are applied in phase such that the output currents of the two mixing processes corresponding to the two injection paths are added constructively at the output frequency $\omega o$ and the overall injection efficiency is therefore increased. A differential buffer circuit with dual injection is proposed. Equivalent circuit modeling of the dual injection buffer and mathematical analysis of locking range enhancement are presented. The core ring oscillator consists of 4 stages of the dual injection buffers. It is fabricated in a 65 nm CMOS technology and consumes less than 2 mW with supply voltage of 1.2 V. Its locking range is from 1.2 to 20.7 GHz without any tuning at 0 dBm injection power level. The proposed ILFD is compact with the core only occupying 15 $\mu$ m $\,\times\,$ 30 $\mu$ m and does not need any extra controls, making it suitable for integrated wideband phase locked loop.