InGaZnO Thin-film Transistors Research Articles

Flexible Self-Aligned Amorphous InGaZnO Thin-Film Transistors With Submicrometer Channel Length and a Transit Frequency of 135 MHz

Flexible large area electronics promise to enable new devices such as rollable displays and electronic skins. Radio frequency (RF) applications demand circuits operating in the megahertz regime, which is hard to achieve for electronics fabricated on amorphous and temperature sensitive plastic substrates. Here, we present self-aligned amorphous indium-gallium-zinc oxide-based thin-film transistors (TFTs) fabricated on free-standing plastic foil using fabrication temperatures . Self-alignment by backside illumination between gate and source/drain electrodes was used to realize flexible transistors with a channel length of 0.5 μm and reduced parasitic capacities. The flexible TFTs exhibit a transit frequency of 135 MHz when operated at 2 V. The device performance is maintained when the TFTs are bent to a tensile radius of 3.5 mm, which makes this technology suitable for flexible RFID tags and AM radios.

Improved performances in low-voltage-driven InGaZnO thin film transistors using a SiO2 buffer layer insertion

In this paper, we report the device characteristics of indium gallium zinc oxide (IGZO) thin film transistors (TFTs) with high-κ lanthanum aluminate (LaAlO3) based gate insulators. The IGZO TFT with single LaAlO3 gate insulator has an operation voltage as low as 1.5 V but suffers a low on-off-state drive current ratio (Ion/Ioff) of 1×103, a large subthreshold swing (SS) of 0.405 V/dec and a small field effect mobility (μFE) of 0.84 cm2/V sec. Inserting a SiO2 buffer layer between IGZO active channel layer and LaAlO3 gate insulator results in a reduced effective dielectric constant but with significant improved characteristics including a high Ion/Ioff of 6.2×104, a small SS of 0.113 V/dec and a large μFE of 5.2 cm2/V sec. Such good performances can be attributed to the lowered gate leakage and reduced interface trap issue owing to the smooth SiO2 buffer layer insertion.

Influence of the InGaZnO channel layer thickness on the performance of thin film transistors

We report on the electrical properties of bottom-gate InGaZnO (IGZO) thin film transistors (TFTs) with different channel layer thicknesses. The IGZO channel layer with thickness varied from 25 to 120nm were deposited by radio frequency sputtering. Al2O3 films were deposited on highly-doped n-Si substrate by atomic layer deposition (ALD) as gate insulator in this work. The influence of the IGZO channel layer thickness on the performance of TFTs is studied. The performance of devices is found to be thickness dependent. The best performance of devices is obtained from a 58nm thick IGZO TFT, which shows a field-effect mobility in the saturation region of 6.2cm2/Vs, a threshold voltage of 2.1V, an Ion/Ioff ratio of approximately 6.4×107, and a subthreshold swing of 0.6V/dec.

Modulation of Interface and Bulk States in Amorphous InGaZnO Thin-Film Transistors with Double Stacked Channel Layers

A high-performance amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) was achieved using a double stacked channel layer (DSCL). An oxygen-poor IGZO film was deposited in pure argon ambient as a buffer layer to prevent oxygen plasma bombardment and improve device performance. An oxygen-rich IGZO film was then deposited on top of that buffer layer to modulate device stability. With this structure, an interface with low oxygen-plasma-induced damage and few oxygen vacancies in the bulk was achieved using DSCL, leading to a higher stability of the threshold voltage.

A comparative study on device degradation under a positive gate stress and hot carrier stress in InGaZnO thin film transistors

The device degradations under a positive gate stress and hot carrier stress in InGaZnO thin film transistors have been compared experimentally. After hot carrier stress, the transfer curves were shifted positively just like after a positive gate stress, and thus the threshold voltage was increased. The increase of the threshold voltage is more significant after hot carrier stress than a positive gate stress. The recovery experiment proves that the increase of the threshold voltage after hot carrier stress is due to the electron trapped charges in the gate dielectrics. The threshold voltage shifts were enhanced for narrow devices under a positive gate stress and hot carrier stress. One can predict the device degradation by monitoring the gate current.

High temperature-induced abnormal suppression of sub-threshold swing and on-current degradations under hot-carrier stress in a-InGaZnO thin film transistors

This letter investigates the effect of temperature on hot-carrier stress-induced degradation behavior in InGaZnO thin film transistors. After hot-carrier stress at 25 °C, serious on-current and subthreshold swing degradations are observed due to trap state generation near the drain side. For identical stress performed at elevated temperatures, current degradation in the I-V transfer curve under reverse mode is gradually suppressed and the anomalous hump in the gate-to-drain capacitance-voltage curve becomes more severe. These suppressed degradations and the more severe hump can be both attributed to hole-trapping near the drain side due to high drain bias at high temperature.

(Invited) Negative-Bias with Illumination Stress Induced State Creation in Amorphous InGaZnO Thin-Film Transistor

Hysteresis of InGaZnO thin-film transistor (IGZO TFT) under negative-bias with illumination stress (NBIS) was investigated using double sweeping gate voltage (VGS) mode. We found that hysteresis of IGZO TFT was significantly enlarged by the NBIS with large negative gate voltage stress. On-current and S value in forward measurements started to show degradation under large-negative VGS stress due to acceptor-like defect creation; on the other hand, transfer curves in reverse measurements shifted to a positive VGS direction without S degradation. As a result of NBIS degradation, huge hysteresis can be observed. To explain the change in hysteresis under NBIS, degradation model consisting of acceptor-like bistable defects is proposed.

Influence of channel layer and passivation layer on the stability of amorphous InGaZnO thin film transistors

The electrical stability of amorphous InGaZnO (a-IGZO) TFTs with three different channel layers was investigated. Compared with the single channel layer, the a-IGZO TFT with double stacked channel layer showed the lowest threshold voltage shift with slightly change in field effect mobility and sub-threshold swing under positive and negative gate bias stress tests. Moreover, sputtered SiNx thin film was served as passivation layer where the Vth shift in bias stress effect evidently became less. It was found that the passivated a-IGZO TFT with double stacked channel layer still exhibited the best stability. The results prove that the stability of a-IGZO TFTs can be effectively improved by using double stacked channel layer and passivation layer.

Mobility enhancement in amorphous InGaZnO thin-film transistors by Ar plasma treatment

The effects of Ar plasma treatment on the back-channel of amorphous InGaZnO (a-IGZO) thin-film transistors are investigated. A decrease in metallic ion-oxygen bonding in the Ar plasma-treated a-IGZO channel layer was observed by X-ray photoelectron spectroscopy (XPS) depth profile analysis. An increase in the channel charge carrier concentration is estimated from the increased oxygen vacancy atomic ratio using XPS curve decomposition analysis. The plasma-treated area of the a-IGZO back-channel is varied with a photoresist screening layer with a varied open window length (Lp). From the Lp-dependent channel resistance analysis, a carrier concentration-dependent field-effect mobility enhancement is observed.

Comparative Study of Device Performance and Reliability in Amorphous InGaZnO Thin-Film Transistors with Various High-k Gate Dielectrics

A comparative study of the electrical characteristics and device instabilities in InGaZnO thin-film transistors (IGZO-TFTs) with four different high-k gate dielectrics (Al2O3, HfO2, Ta2O5, and ZrO2) has been conducted. High-k gate dielectrics have a sufficiently low leakage current for the gate insulator of IGZO-TFTs and ZrO2 has the highest dielectric constant, followed by Ta2O5, HfO2, and Al2O3. However, the charge trapping in high-k gate dielectrics induced the bias stress instability and degradation of IGZO-TFTs over time. In particular, the positive bias stress (PBS) and positive bias temperature stress (PBTS) caused a large positive threshold voltage (Vth) variation due to electron trapping, while the negative bias stress (NBS) and negative bias temperature stress (NBTS) brought about a much smaller Vth shift. In particular, the Al2O3 and HfO2 gate insulators have significant threshold voltage shifts for the PBS and PBTS measurements. Among the four different high-k gate dielectrics, ZrO2 is the most promising high-k gate dielectric for the IGZO-TFTs because of its high dielectric constant, low subthreshold swing, high mobility, large drive current, small hysteresis, and high on/off current ratio.

P.18: Effects of Interface and Bulk States on the Stability of Amorphous InGaZnO Thin Film Transistors under Gate Bias and Temperature Stress

AbstractThe gate bias and temperature instability of InGaZnO TFTs were improved by adopting double stacked channel layer (DSCL). The mechanism of Vth shift under stress was studied by this structure. An interface with of less oxygen plasma damaging and lower oxygen vacancies in bulk were achieved by DSCL, resulting in a higher stability of Vth.

P.12: Development of Post‐annealing Method for Flexible Oxide TFTs Application

AbstractMicrowave annealing was used instead of furnace annealing to post‐treat a nitridated amorphous InGaZnO thin film transistor (a‐IGZO:N TFT), and obviously improved its electrical performance and reliability. This performance of a‐IGZO:N TFT with microwave annealing process of 300s is well competitive with its counterpart with furnace annealing at 350°C for 1 hr. Owing to its low thermal budget and selective heating to materials of interest, microwave annealing is highly promising for flexible oxide TFTs application.

P.62: Effects of Amorphous InGaZnO Thin Film Transistors with Various Buffer Layers on Polyimide Substrate Under Negative Bias‐temperature Stresses

AbstractBuffer layers on flexible substrates have strongly affected to electrical performance and instability in oxide TFTs. The oxide TFT on proper buffer layer/PI substrate showed better electrical performance than that on other buffer layers because the buffer layer with high gas diffusion barrier properties can suppress to generate defect states in semiconductor and/or interface from hydrogen and water penetration. The origins of flexible oxide TFT instabilities were systematically investigated by using in‐situ/ex‐situ measurement and chemical/physical analysis.

A Flexible IGZO Thin-Film Transistor With Stacked ${\rm TiO}_{2}$-Based Dielectrics Fabricated at Room Temperature

This letter demonstrates the feasibility of full room temperature InGaZnO thin-film transistor (TFT) using trilayer gate dielectric on flexible substrate. Through integrating high-κ SiO2/TiO2/SiO2 (STS) gate-stack as well as InGaZnO channel thickness modulation, the resulting flexible indium-gallium-zinc oxide (IGZO)/STS TFTs show low threshold voltage of 0.5 V, small subthreshold swing of 0.129 V/decade, high field effect mobility of 76 cm2/Vs , and good ION/IOFF ratio of 6.7×105, which have the potential for the application of high-resolution flexible display.

52.4: Distinguished Paper: Electrical Properties of Amorphous InGaZnO Thin‐Film Transistors Prepared by Magnetron Sputtering with Using Kr and Xe Instead of Ar

AbstractHeavier noble gases of Kr and Xe instead of the lighter Ar during the magnetron‐sputtering deposition of amorphous indium—gallium‐zinc oxide films are introduced in fabricating their thin‐film transistors. Higher field effect mobility can be obtained by introducing heavier noble gases, while gate bias stability shows no significant difference between gas species. Raman spectroscopic analysis suggests that the disordered structure in the film is suppressed by introducing heavier noble gases. These results suggest that the introduction of heavy noble gases can reduce damage to film by ion bombardment during the sputtering depositions, resulting in the improvement of field effect mobility.

Effects of Mg doping on the gate bias and thermal stability of solution-processed InGaZnO thin-film transistors

Mg-doped IGZO TFTs showed improved TFT performance and thermal stability due to fewer oxygen deficiencies and less interface electron trapping. • We fabricated Mg-doped IGZO TFTs with improved performance using solution-process. • Mg doping reduced the oxygen deficiencies and less interface electron trapping of a-IGZO films. • Mg dope-TFT showed high mobility of 2.35 cm 2 /V s and an on–off current ratio over 10 6 . • For better device stability (gate-bias and thermal stability) was proved. The effects of magnesium (Mg) doping (molar ratio Mg/Zn = (0–10 at.%)) on solution-processed amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) grown using the sol–gel method are investigated. TFT devices fabricated with Mg-doped films showed an improved field-effect mobility of 2.35 cm 2 /V s and a subthreshold slope (S) of 0.42 V/dec compared to those of an undoped a-IGZO TFT (0.73 cm 2 /V s and 0.74 V/dec, respectively), and an on–off current ratio of over 10 6 . Moreover, the 5 at.% Mg-doped TFT device showed improved gate bias and thermal stability due to fewer oxygen deficiencies, smaller carrier concentration, and less interface electron trapping in the a-IGZO films.

Impact of UV/O3 treatment on solution-processed amorphous InGaZnO4 thin-film transistors

Ultraviolet–ozone (UV/O3) treatment was adopted to the fabrication of solution-processed amorphous In–Ga–Zn–O thin-film transistors (TFTs), with metal composition of In:Ga:Zn = 1:1:1 represented by InGaZnO4. By applying UV/O3 treatment In–Ga–Zn–O gel films, their condensation was notably enhanced through decomposition of organic- and hydrogen-based elements, which drastically improved the quality of the amorphous InGaZnO4 films. As a result, high TFT performance, with values of on/off ratio, 108; subthreshold swing, 150 mV/decade; threshold voltage, 9.2 V; and field-effect mobility, 5.1 cm2 V−1 s−1, was achieved.

High-performance low-temperature solution-processed InGaZnO thin-film transistors via ultraviolet-ozone photo-annealing

Ultraviolet (UV)-ozone photo-annealing was applied to fabricate low-temperature high-performance solution-processed thin-film transistors (TFTs). With UV-ozone treatment at the optimal temperature of 300 °C, TFT devices showed an improved field-effect mobility of 1.73 cm2 V−1 s−1, a subthreshold slope (S) of 0.32 V dec−1, an on/off-current ratio greater than 1.3 × 107, and good operational bias-stress stability compared to those of InGaZnO TFT devices fabricated with only a conventional thermal-annealing process. The results of X-ray photoelectron spectroscopy and the maximum density of the surface states (Ns) confirm that the device improvement originates from reduced oxygen-related defects and improved electron trapping due to UV-ozone irradiation.

Structural and electrical characteristics of high-κ ErTixOy gate dielectrics on InGaZnO thin-film transistors

In this paper, we investigated the structural properties and electrical characteristics of high-κ ErTixOy gate dielectrics on indium-gallium-zinc oxide thin-film transistors (IGZO TFTs). We used X-ray diffraction, X-ray photoelectron spectroscopy, and atomic force microscopy to investigate the structural and morphological features of these dielectric films after they had been subjected to annealing at various temperatures. The high-κ ErTixOy IGZO TFT device annealed at 400°C exhibited better electrical characteristics in terms of a large field-effect mobility (8.24cm2/V-s), low threshold voltage (0.36V), small subthreshold swing (130mV/dec), and high Ion/off ratio(3.73×106). These results are attributed to the reduction of the trap states and oxygen vacancies between the ErTixOy film and IGZO active layer interface during high-temperature annealing in oxygen ambient. The reliability of voltage stress also can be improved by the oxygen annealing at 400°C.

Charge-trap effects of 2D DNA nanostructures implanted in solution-processed InGaZnO thin-film transistor

A double crossover (DX) tile-based 2D DNA nanostructure was fabricated and implanted successfully in solution-processed InGaZnO thin film transistor. Observations indicated that the DNA nanostructure plays an important role as a trap charge centre under high electric field in the memory device. At positive gate voltage the memory device with the DNA shows appreciable trapped charge and at negative gate voltage reveals detrapped negative charge characteristics. Consequently, various dimensional DNA nanostructures may play a central role in nanoscale devices and applications in the near future.