InGaZnO Thin-film Transistors Research Articles

Suppression of Degradation Induced by Negative Gate Bias and Illumination Stress in Amorphous InGaZnO Thin-Film Transistors by Applying Negative Drain Bias

The effect of drain bias (V(DS)) on the negative gate bias and illumination stress (NBIS) stability of amorphous InGaZnO (a-IGZO) thin-film transistors was investigated using a double-sweeping gate voltage (V(GS)) mode. The variation in the transfer characteristics was explored using current-voltage and capacitance-voltage characteristics. In the initial stage (<1000 s) of NBIS with grounded V(DS) (V(GS) = -40 V and V(DS) = 0 V), the transfer characteristics shifted negatively with an insignificant change in the subthreshold swing (SS) because of hole trapping at an IGZO/gate insulator interface. On the other hand, on-current degradation was observed and was accelerated in the forward measurement as the NBIS duration increased. The results indicated that NBIS induced donor-like defects near the conduction band; however, the transfer curves in the reverse measurement shifted positively without on-current and SS degradations. It was found that the degradations were enhanced by applying a positive V(DS) bias (V(GS) = -40 V and V(DS) = 40 V); in contrast, they could be reduced by applying a small negative V(DS) of V(DS) > V(GS) (V(GS) = -40 V and V(DS) = -20 V). Furthermore, it was confirmed that the NBIS degradations could be suppressed by applying a large negative V(DS) bias of V(DS) < V(GS) (V(GS) = -40 V and V(DS) = -60 V) during NBIS.

Amorphous InGaZnO Thin Film Transistors with Wet-Etched Ag Electrodes

Amorphous InGaZnO Thin Film Transistors with Wet-Etched Ag Electrodes

Effect of Temperature and Electric Field on Degradation in Amorphous InGaZnO TFTs Under Positive Gate and Drain Bias Stress

The mechanism of the electrical degradation in amorphous InGaZnO thin-film transistors under a positive gate and drain bias stress is investigated. The stress tests under various combinations of bias and temperature reveal that the negative shift of transfer curves accompanied by a hump is attributed to not an electric field or heating alone, but the simultaneous effect of them. Furthermore, the mitigated degradation under a pulsed stress of a reduced pulse period from 2 s to 0.1 ms and the difference in output characteristics between a dc sweep and a pulsed sweep measurements imply that self-heating with the high field could be the main cause of the degradation rather than hot-carrier effect.

Effects of combined Ar/O2 plasma and microwave irradiation on electrical performance and stability in solution-deposited amorphous InGaZnO thin-film transistors

We demonstrated the improvement of electrical performance and stability of solution-deposited amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) by combined Ar/O2 plasma and microwave irradiation (MWI) treatment at low temperature. After the combined MWI and Ar/O2 plasma treatments, the bonding between metal and oxygen ions was strengthened, and then the solution-deposited a-IGZO film acted as a semiconductor for transistors. In addition, the Ar/O2 plasma treatment promoted the reliability of solution-deposited a-IGZO TFTs owing to the removal of residual carbon, which easily traps electrons. Consequently, the solution-deposited a-IGZO TFT treated with the combination of Ar/O2 plasma and MWI exhibited excellent electrical stability as well as an improved transfer characteristic. Therefore, the combined Ar/O2 plasma and MWI treatment is a feasible post-treatment to realize flexible electronics with solution-deposited metal oxide thin films.

Effects of Ta incorporation in La2O3 gate dielectric of InGaZnO thin-film transistor

The effects of Ta incorporation in La2O3 gate dielectric of amorphous InGaZnO thin-film transistor are investigated. Since the Ta incorporation is found to effectively enhance the moisture resistance of the La2O3 film and thus suppress the formation of La(OH)3, both the dielectric roughness and trap density at/near the InGaZnO/dielectric interface can be reduced, resulting in a significant improvement in the electrical characteristics of transistor. Among the samples with different Ta contents, the one with a Ta/(Ta + La) atomic ratio of 21.7% exhibits the best performance, including high saturation carrier mobility of 23.4 cm2/V·s, small subthreshold swing of 0.177 V/dec, and negligible hysteresis. Nevertheless, excessive incorporation of Ta can degrade the device characteristics due to newly generated Ta-related traps.

Investigation of on-current degradation behavior induced by surface hydrolysis effect under negative gate bias stress in amorphous InGaZnO thin-film transistors

This study investigates the electrical instability under negative gate bias stress (NGBS) induced by surface hydrolysis effect. Electrical characteristics exhibit instability for amorphous InGaZnO (a-IGZO) Thin Film Transistors (TFTs) under NGBS, in which on-current degradation and current crowding phenomenon can be observed. When the negative gate bias is applied on the TFT, hydrogen ions will dissociate from ZnO-H bonds and the dissociated hydrogen ions will cause electrical instability under NGBS. The ISE-Technology Computer Aided Design simulation tool and moisture partial pressure modulation measurement are utilized to clarify the anomalous degradation behavior.

A study on the degradation mechanism of InGaZnO thin-film transistors under simultaneous gate and drain bias stresses based on the electronic trap characterization

We discuss the device degradation mechanism of amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) under simultaneous gate and drain bias stresses based on the electronic trap characterization results. The transfer curve exhibits an apparent negative shift as the stress time increases, and a formation of hump is observed in the transfer curve after stresses. A notable increase of the frequency dispersion is observed after stresses in both gate-to-drain capacitance–voltage (CGD–VG) and gate-to-source capacitance–voltage (CGS–VG) curves, which implies that the subgap states are generated by simultaneous gate and drain bias stresses, and the damaged location is not limited to the drain side of TFTs. The larger frequency dispersion is observed in CGD–VG curves after stresses in a wider channel device, which implies that the heat is an important factor in the generation of the subgap states under simultaneous gate and drain bias stresses in a-IGZO TFTs. Based on the electronic trap characterization results, we conclude that the impact ionization near the drain side of the device is not a dominant mechanism causing the generation of subgap states and device degradation in a-IGZO TFTs under simultaneous gate and drain bias stresses. The generation of oxygen vacancy-related donor-like traps near the conduction band edge is considered as a possible mechanism causing the device degradation under simultaneous gate and drain bias stresses in a-IGZO TFTs.

Device Instability Under High Gate and Drain Biases in InGaZnO Thin Film Transistors

An experimental investigation of channel-hot-carrier-induced device degradation in indium-gallium-zinc oxide (IGZO) thin-film transistors was undertaken for different stress biases and channel widths. Although there is no shift of the transfer curve after only a positive gate stress, a negative shift of the transfer curve is observed after both positive gate and drain stresses. The decrease in threshold voltage and the increase in the inverse subthreshold slope are observed. The negative shift of the transfer curve may be attributed to the doubly charged oxygen vacancies generated by the injection of the channel hot electrons into the gate dielectric layer. From the measurements with different drain stresses at a constant gate stress, it was found that the device degradation occurred when the lateral electric field reaches a critical value. From device simulations and measurements, it was found that the interface trap charges are located near the source side at high gate stress voltages. On the other hand, they are located near the drain side at lower gate stress voltages. The device degradation was the most significant at the stress condition of V GS = VDS, when the stress VDS is constant. Device degradation increases with channel widths.

Improved Performance of InGaZnO Thin-Film Transistor With HfLaO Gate Dielectric Annealed in Oxygen

We have fabricated an amorphous InGaZnO thin-film transistor with HfLaO gate dielectric, and the influence of annealing the gate dielectric in oxygen on the device characteristics is investigated in detail. It is demonstrated that this annealing treatment can effectively suppress the negative oxide charges. In addition, the effect of this annealing treatment to suppress the acceptor-like border and interface traps has been discovered, which can explain the unusual phenomenon of counterclockwise hysteresis. Accordingly, a record-high saturation carrier mobility of 35.2 cm2/V ·s has been achieved for the device, and its threshold voltage, subthreshold swing, and on-off current ratio are 2.8 V, 0.292 V/dec, and 5.2 ×106, respectively.

Fluorinated InGaZnO Thin-Film Transistor With HfLaO Gate Dielectric

Fluorinated amorphous InGaZnO thin-film transistor with HfLaO gate dielectric has been studied by treating InGaZnO film in a CHF3/O2 plasma. The saturation carrier mobility can be improved from 29.6 cm2/V·s to as high as 39.8 cm2/V·s. In addition, the passivation effect of the fluorination on the dominant donor-like traps at the InGaZnO/HfLaO interface is observed, as reflected by suppression of hysteresis phenomenon and smaller subthreshold swing. Measurement result of low-frequency noise further supports the improvement in electrical properties by the plasma treatment.

Effect of SiOx/SiNx Stacked Gate Dielectric Structure on the Instability of a-IGZO Thin Film Transistors

Among amorphous oxide thin film transistors, amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFT) is currently highlightened because of its advantages such as high mobility, transparent characteristic, flexibility and so on. It is required to ensure the stability of the device under various environments has to be verified before high-volume manufacturing. In this paper, the instability of amorphous InGaZnO TFT depending on the SiOx/SiNx stacked gate dielectric material is investigated through bias and light illumination stress test. Here, the TFT’s instability characteristics are examined by the density of total trap states at the channel/gate dielectric interface (Nit).

Effect of contact material on amorphous InGaZnO thin-film transistor characteristics

Amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) having several metals, namely Ag, Ti, and Mo, as the source and drain electrodes were characterized. TFTs with Ti and Mo electrodes showed drain current–gate voltage characteristics without fluctuation. However, TFTs with Ag electrodes indicated a low noisy on-state current at a large channel length under a low drain–source voltage condition. The source and drain resistances [Rs/d (Ω)] of the TFTs with each of the three metals were calculated from the IDS–VGS characteristics. The Rs/d values of the Ag, Ti, and Mo samples reached 4 × 104, 2 × 104, and 1 × 104 Ω, respectively. This implies that a spatial potential barrier exists at the a-IGZO/Ag interface and that the resistance of the potential barrier changes with the application of gate voltage.

Effects of geometrically extended contact area on electrical properties in amorphous InGaZnO thin film transistors

To elucidate the effect of the contact geometry on the device performances, the amorphous InGaZnO field effect transistors with different contact areas were fabricated and compared by the transmission line method. Extended contact-area devices were found to have better electrical performances in field effect mobility and subthreshold swing than those of bar-shaped reference devices. These improvements in the device characteristics resulted from a significantly reduced contact resistance (Rc). From the comparison of specific contact resistivity and transfer length (LT), the relationship between Rc and contact area including the contact width and the LT was established and demonstrated that Rc is controllable by optimizing the contact area geometry.

The effects of buffer layers on the performance and stability of flexible InGaZnO thin film transistors on polyimide substrates

We demonstrated the fabrication of flexible amorphous indium gallium zinc oxide thin-film transistors (TFTs) on high-temperature polyimide (PI) substrates, which were debonded from the carrier glass after TFT fabrication. The application of appropriate buffer layers on the PI substrates affected the TFT performance and stability. The adoption of the SiNx/AlOx buffer layers as water and hydrogen diffusion barriers significantly improved the device performance and stability against the thermal annealing and negative bias stress, compared to single SiNx or SiOx buffer layers. The substrates could be bent down to a radius of curvature of 15 mm and the devices remained normally functional.

InGaZnO thin-film transistors with back channel modification by organic self-assembled monolayers

InGaZnO (IGZO) thin-film transistors (TFTs) with back channel modified by different kinds of self-assembled monolayers (SAMs) were fabricated. The mobility and electrical stability of the IGZO-TFTs were greatly improved after SAM-modification, owing to the good interface coupling and less water adsorption-desorption effect on the IGZO surface. Meanwhile, the octadecyltriethoxysilane (OTES) treated IGZO-TFT exhibited a higher mobility of 26.6 cm2 V−1 s−1 and better electrical stability compared to the octadecanethiol (ODT) treated one, which was attributed to the formation of a more compact and steady SAM on the IGZO surface after OTES treatment.

Comparative Study of ZrO&lt;SUB&gt;2&lt;/SUB&gt; and HfO&lt;SUB&gt;2&lt;/SUB&gt; as a High-&lt;I&gt;k&lt;/I&gt; Dielectric for Amorphous InGaZnO Thin Film Transistors

Comparative Study of ZrO&lt;SUB&gt;2&lt;/SUB&gt; and HfO&lt;SUB&gt;2&lt;/SUB&gt; as a High-&lt;I&gt;k&lt;/I&gt; Dielectric for Amorphous InGaZnO Thin Film Transistors

Effect of drain bias on negative gate bias and illumination stress induced degradation in amorphous InGaZnO thin-film transistors

The effect of drain bias (VDS) on the negative gate bias and illumination stress (NBIS) stability of amorphous InGaZnO thin-film transistors (a-IGZO TFTs) was investigated. The evolution of transfer characteristics was explored in terms of NBIS duration. In the initial stage (<1000 s) of the NBIS with grounded VDS, the transfer characteristics negatively shifted with an insignificant change in subthreshold swing owing to hole trapping at an IGZO/gate insulator interface. On the other hand, on-current degradation was observed and was enhanced as NBIS duration increased. The results indicate that NBIS-induced defects were created above the Fermi level energy. NBIS-induced defect creation was enhanced at a positive VDS bias of 40 V. However, it was found that NBIS-induced defect creation can be suppressed by a negative VDS bias, as the absolute value of VDS was larger than that of gate voltage during NBIS.

Negative Bias and Illumination Stress Induced Electron Trapping at Back-Channel Interface of InGaZnO Thin-Film Transistor

Double-sweeping gate voltage mode and positive gate pulse mode were used to investigate the mechanism of negative bias and illumination stress (NBIS) induced hysteresis in bottom-gate InGaZnO TFTs. Threshold voltages (Vth) in reverse measurement shifted positively and were well fitted to a stretched-exponential equation under various gate bias stress conditions. “Hump” effect appeared in the forward measurement and hysteresis gradually increased with stress time. The results indicate that trapped electrons at back interface, trapped holes at front interface and the generation of donor-like states in IGZO bulk channel were reasons for instability of IGZO TFTs under NBIS. © 2014 The Electrochemical Society. [DOI: 10.1149/2.010403ssl] All rights reserved.

Improvements in passivation effect of amorphous InGaZnO thin film transistors

The performance of amorphous InGaZnO thin film transistors (a-IGZO TFTs) degrades apparently due to “passivation effect”, i.e. back-channel plasma damage from passivation layer deposition. In this letter two effective measures were taken to improve this effect. Double-stacked channel layer (DSCL), a novel active-layer structure, was proposed with which a-IGZO TFTs might suffer less plasma damage from passivation layer deposition, as was confirmed by investigation with high resolution transmission electron microscope (SRTEM). Moreover, two-stage annealing (TSA) method showed more advantages over conventional heat treatment at one fixed temperature in curing back-channel plasma damage caused by passivation deposition. The a-IGZO TFTs, Combined with these two improving methods, exhibited fine performance parameters (μFE of 2.0cm2/Vs, SS of 1.5V/decade, Ion/Ioff of 106 and Vth of 1.5V) as well as satisfactory ambient stability, meeting the requirements for their applications in flat panel displays.

Advanced Cu Interconnection via Electroless-Plated Ni Interlayer on the Gate of Oxide Thin-Film Transistors

We demonstrate Cu interconnection/electrode formation in bottom gate InGaZnO (IGZO) thin-film transistors (TFTs), so that conductivity may be enhanced and a more advanced display panel may replace conventional Al and Mo. To date, the development of a Cu interconnection/electrode has been hampered by the poor adhesion between Cu and SiO2, the main gate insulator (GI) for IGZO TFTs. However, our research shows that an electro-less selective plating of Na-free Ni on pre-patterned Cu electrodes can make this goal obtainable. According to the bias- and photo-stability measurements, our IGZO TFT with Na-free Ni-plated Cu electrodes are much more stable than IGZO TFTs prepared with conventional methods such as NaOH-induced Ni plating on Cu and H-containing SiNx/SiO2 double layer GI on Cu. Moreover, the conventionally-prepared devices were also photo-sensitive due to the Na or H ions diffused into the GI/channel interface area. We conclude that electro-less plating of Na-free Ni on Cu is a promising approach for advanced future display panel by oxide TFTs.