Effect of drain bias on negative gate bias and illumination stress induced degradation in amorphous InGaZnO thin-film transistors

Abstract

The effect of drain bias (VDS) on the negative gate bias and illumination stress (NBIS) stability of amorphous InGaZnO thin-film transistors (a-IGZO TFTs) was investigated. The evolution of transfer characteristics was explored in terms of NBIS duration. In the initial stage (<1000 s) of the NBIS with grounded VDS, the transfer characteristics negatively shifted with an insignificant change in subthreshold swing owing to hole trapping at an IGZO/gate insulator interface. On the other hand, on-current degradation was observed and was enhanced as NBIS duration increased. The results indicate that NBIS-induced defects were created above the Fermi level energy. NBIS-induced defect creation was enhanced at a positive VDS bias of 40 V. However, it was found that NBIS-induced defect creation can be suppressed by a negative VDS bias, as the absolute value of VDS was larger than that of gate voltage during NBIS.