Inductively Coupled Plasma Chemical Vapor Deposition Research Articles

Nanocrystalline Silicon Thin-Film Transistor Fabricated without Substrate Heating for Flexible Display

We fabricated nanocrystalline silicon (nc-Si) thin-film transistors (TFTs) without any substrate heating. High quality nc-Si and silicon dioxide films were deposited at room temperature employing an inductively coupled plasma chemical vapor deposition (ICP-CVD) system. For the nc-Si film, a crystalline phase was grown as a columnar structure and the crystalline volume fraction was 27%. On the silicon dioxide film, hydrogen plasma post-treatment was performed, and the electrical characteristics of silicon dioxide film improved owing to charge reduction and the annealing effect. The nc-Si and silicon dioxide films were used for the fabrication of nc-Si TFTs without substrate heating. Although there was no external heating, a mobility of 6.42 cm2·V-1·s-1 was achieved. This result indicates that nc-Si TFTs fabricated without substrate heating may be a suitable devices for a flexible display.

Hydrogenated Amorphous Silicon Layer Formation by Inductively Coupled Plasma Chemical Vapor Deposition and Its Application for Surface Passivation of p-Type Crystalline Silicon

The satisfactory surface passivation properties of hydrogenated amorphous silicon (a-Si:H) prepared by inductively coupled plasma chemical vapor deposition (ICP-CVD) at a low temperature (400 °C) on p-type crystalline silicon wafers are reported. Certain parameters, such as SiH4/H2 ratio, annealing temperature, film thickness, and substrate temperature, were varied to determine their optimal levels. Completely amorphous layers with a broad transverse optic (TO) mode peak at approximately 480 cm-1 were identified by Raman spectroscopy, and an optical band gap of approximately 1.6 eV was determined from optical absorption data. A maximum carrier lifetime of 53 µs for an a-Si:H thickness of 15 nm and an annealing temperature of 450 °C was measured for 525-µm-thick p-type crystalline silicon (c-Si) substrates with a resistivity in the range of 1–20 Ω cm by the quasi-steady-state photoconductance (QSSPC) method. The lowest value of interface trapped charge density (Dit) of approximately 3.34 ×1011 cm-2 eV-1 was estimated by capacitance–voltage (C–V) measurement using a metal–insulator–semiconductor (MIS) structure. Furthermore, simple processing with satisfactory results can be achieved with substrate heating at 400 °C during deposition. The optimal conditions of a SiH4/H2 gas ratio of 1/1 and a substrate temperature of 400 °C were implemented for a passivation layer thickness of 5 nm.

Low-temperature deposition of highly crystallized silicon films on Al-coated polyethylene napthalate by inductively coupled plasma CVD

We prepared highly crystallized silicon films on Al-coated polyethylene napthalate (PEN) substrates using inductively coupled plasma chemical vapor deposition (ICP-CVD) at low temperature with a mixture of SiH 4/H 2 as the source gas. The microstructure of the films was evaluated using Raman spectroscopy, scanning electron microscope (SEM) and transmission electron microscopy (TEM). The effects of deposition parameters on the crystallinity of silicon films on bare and Al-coated PEN were systematically investigated. Compared to the films deposited on bare PEN, an obvious phase transition from amorphous to crystalline occurred when decreasing the SiH 4 dilution ratio [ R = [SiH 4]/([SiH 4] + [H 2])] to 4% for the films on Al-coated substrates. With increasing the input power from 300 W to 400 W, the crystallinity of the films on bare and Al-coated PEN are both improved at a low temperature as low as 85 °C. The film on Al-coated PEN shows excellent crystallization with crystalline fraction of 82% and preferred orientation of (1 1 1). It has been found that the interaction between precursors and aluminum layers plays an important role and there should exist a different crystallization mechanism as compared to traditional annealing crystallization of amorphous Si/Al layer in the crystallization process of silicon films on Al-coated PEN at low temperature.

Residual stress on nanocrystalline silicon thin films deposited under energetic ion bombardment by using internal ICP-CVD

Nano/microcrystalline silicon thin films were deposited using an internal-type, inductively coupled, plasma-chemical vapor deposition (ICP-CVD) at room temperature by varying the bias power to the substrate. The structural characteristics of the deposited thin film were investigated. The deposition rate was increased by the application of a small RF bias power of 30 W (12.56 MHz), but was then decreased as the bias power was increased above 30 W. In addition, the application of bias power generally increased the residual compressive stress, which was attributed to the increased defect formation in the thin film due to the formation of interstitial atoms. The crystalline volume fraction was also decreased with increasing bias power. However, in the low bias power range of 0–60 W, the compressive stress in the deposited thin film was in the range of − 34 to − 77 MPa, which was lower than the residual stress in the range of − 150 to − 1050 MPa that is observed for the nano/microcrystalline silicon thin films deposited by capacitively coupled plasma.

수치모델을 이용한 ICP-CVD 장치의 증착 균일도 해석

Numerical analysis is done to investigate which would be the most influencing process parameter in determining the uniformity of deposition thickness in TiN ICP-CVD(inductively coupled plasma chemical vapor deposition). Two configurations of ICP antenna are modeled; side and top planar. Side and top gas inlets are considered with each ICP antenna geometries. Precursor for TiN deposition was TDMAT(Tetrakis Diethyl Methyl Amido Titanium). Two step volume dissociation of TDMAT is used and absorption, desorption and deposition surface reactions are included. Most influencing factors are H and N concentration dissociated by electron impact collisions in plasma volume which depends on the relative positions of gas inlet and ICP antenna generated hot plasma region. Low surface recombination of N shows hollow type concentration, but H gives a bell type distribution. Film thickness at substrate edges is sensitive to gas flow rate and at high pressures getting more dependent on flow characteristics.

60 nm 와 20 nm 두께의 수소화된 비정질 실리콘에 따른 저온 니켈실리사이드의 물성 변화

ICP-CVD를 사용하여 수소화된 비정질 실리콘(a-Si:H)을 60 nm 또는 20 nm 두께로 성막 시키고, 그 위에 전자총증착장치(e-beam evaporator)를 이용하여 30 nm Ni 증착 후, 최종적으로 30 nm Ni/(60 또는 20 nm a-Si:H)/200 nm <TEX>$SiO_2$</TEX>/single-Si 구조의 시편을 만들고 <TEX>$200{\sim}500^{\circ}C$</TEX> 사이에서 <TEX>$50^{\circ}C$</TEX>간격으로 40초간 진공열처리를 실시하여 실리사이드화 처리하였다. 완성된 니켈실리사이드의 처리온도에 따른 면저항값, 상구조, 미세구조, 표면조도 변화를 각각 사점면저항측정기, HRXRD, FE-SEM과 TEM, SPM을 활용하여 확인하였다. 60 nm a-Si:H 기판 위에 생성된 니켈실리사이드는 <TEX>$400^{\circ}C$</TEX>이후부터 저온공정이 가능한 면저항값을 보였다. 반면 20 nm a-Si:H 기판 위에 생성된 니켈실리사이드는 <TEX>$300^{\circ}C$</TEX>이후부터 저온공정이 가능한 면저항값을 보였다. HRXRD 결과 60 nm 와 20 nm a-Si:H 기판 위에 생성된 니켈실리사이드는 열처리온도에 따라서 동일한 상변화를 보였다. FE-SEM과 TEM 관찰결과, 60 nm a-Si:H 기판 위에 생성된 니켈실리사이드는 저온에서 고저항의 미반응 실리콘이 잔류하고 60 nm 두께의 니켈실리사이드를 가지는 미세구조를 보였다. 20 nm a-Si:H 기판위에 형성되는 니켈실리사이드는 20 nm 두께의 균일한 결정질 실리사이드가 생성됨을 확인하였다. SPM 결과 모든 시편은 열처리온도가 증가하면서 RMS값이 증가하였고 특히 20 nm a-Si:H 기판 위에 생성된 니켈실리사이드는 <TEX>$300^{\circ}C$</TEX>에서 0.75 nm의 가장 낮은 RMS 값을 보였다. 60 nm and 20 nm thick hydrogenated amorphous silicon(a-Si:H) layers were deposited on 200 nm <TEX>$SiO_2$</TEX>/single-Si substrates by inductively coupled plasma chemical vapor deposition(ICP-CVD). Subsequently, 30 nm-Ni layers were deposited by an e-beam evaporator. Finally, 30 nm-Ni/(60 nm and 20 nm) a-Si:H/200 nm-<TEX>$SiO_2$</TEX>/single-Si structures were prepared. The prepared samples were annealed by rapid thermal annealing(RTA) from <TEX>$200^{\circ}C$</TEX> to <TEX>$500^{\circ}C$</TEX> in <TEX>$50^{\circ}C$</TEX> increments for 40 sec. A four-point tester, high resolution X-ray diffraction(HRXRD), field emission scanning electron microscopy(FE-SEM), transmission electron microscopy(TEM), and scanning probe microscopy(SPM) were used to examine the sheet resistance, phase transformation, in-plane microstructure, cross-sectional microstructure, and surface roughness, respectively. The nickel silicide from the 60 nm a-Si:H substrate showed low sheet resistance from <TEX>$400^{\circ}C$</TEX> which is compatible for low temperature processing. The nickel silicide from 20 nm a-Si:H substrate showed low resistance from <TEX>$300^{\circ}C$</TEX>. Through HRXRD analysis, the phase transformation occurred with silicidation temperature without a-Si:H layer thickness dependence. With the result of FE-SEM and TEM, the nickel silicides from 60 nm a-Si:H substrate showed the microstructure of 60 nm-thick silicide layers with the residual silicon regime, while the ones from 20 nm a-Si:H formed 20 nm-thick uniform silicide layers. In case of SPM, the RMS value of nickel silicide layers increased as the silicidation temperature increased. Especially, the nickel silicide from 20 nm a-Si:H substrate showed the lowest RMS value of 0.75 at <TEX>$300^{\circ}C$</TEX>.

Highly Stable Bottom-Gate Nanocrystalline Silicon Thin Film Transistor Fabricated Employing ICP-CVD

Bottom-gate nanocrystalline silicon (nc-Si) thin film transistors (TFTs) were fabricated and evaluated their characteristics and electrical stability under various stress condition. nc-Si with high crystallinity was deposited employing Inductively coupled plasma chemical vapor deposition(ICP-CVD) system. We employed helium gas diluted deposition and all the process temperature was kept under 350oC. We fabricated conventional inverted-staggered nc-Si TFTs. Fabricated nc-Si TFTs showed fine electrical characteristics, such as electrical mobility of 0.64~0.77 cm2/V⋅sec. We investigated its stability through constant-voltage stress and constant-current stress. The threshold voltage shift after 30,000 seconds gate bias (10V) stress was only 0.098V, which is considerably less compared to a-Si:H TFT. Under the static current stress condition, the threshold voltage of the nc-Si TFT was shifted less than that of a-Si:H TFT. It demonstrates that nc-Si TFT exhibit better stability than conventional a-Si:H TFT.

Preparation of Phosphorus Doped Hydrogenated Microcrystalline Silicon Thin Films by Inductively Coupled Plasma Chemical Vapor Deposition and Their Characteristics for Solar Cell Applications

Intrinsic and phosphorus-doped hydrogenated microcrystalline silicon (microc-Si:H) films were prepared using inductively coupled plasma chemical vapor deposition (ICP-CVD) method. Structural, electrical and optical properties of these films were studied as a function of silane concentration, ICP source power and PH3/SiH4 gas ratio. Characterization of these films from Raman spectroscopy and X-ray diffraction revealed that the conductive film exists in microcrystalline phase embedded in an amorphous network. The condition of electrical properties (sigma(d): approximately 10(-7) S/cm, sigma(ph): approximately 10(-4) S/cm) and activation energy (0.55 eV), satisfied with properties of intrinsic microc-Si:H, was obtained at 1200 W of ICP power and 2% of silane concentration, respectively. At PH3/SiH4 gas ratio of 0.09%, dark conductivity has a maximum value of approximately 18.5 S/cm and optical bandgap also a maximum value of approximately 2.39 eV. The deposition rate was not satisfactory (4.9 angstroms/s) at same condition.

Direct growth of carbon nanotubes on a micro-sized cobalt tip and characterization of electron-emission properties

Carbon nanotubes (CNTs) are synthesized directly on an electrically conducting cobalt (Co) tip of 1 μm in diameter, without any additional buffer or catalyst layer, through inductively coupled plasma-chemical vapor deposition (ICP-CVD). The nanostructures, morphologies, and crystalline structures of all the CNTs are analyzed through field emission SEM, high-resolution TEM, and Raman spectroscopy. Compared with the conventional emitter, which has a configuration of CNTs/Co(catalyst)/TiN(buffer)/W-tip, the CNTs/Co-tip field emitter proposed in this work show a noticeably improved performance in the electron-emission characteristics as well as in the stability of the emission current due to prolonged operation (up to 50 h).

Investigation on the Surface Passivation of Intrinsic a-Si:H Thin Films Prepared by Inductively Coupled Plasma-Chemical Vapor Deposition for Heterojunction Solar Cell Applications

Intrinsic a-Si:H thin films, which can have passivation functions on the surface of crystalline Si, were deposited by inductively coupled plasma chemical vapor deposition (ICP-CVD). The properties of the films were investigated at deposition temperatures ranging from 50 to 400 degrees C. The Si--H stretching mode at 2000 cm(-1), which indicates good film quality, was found in the range of 150-400 degrees C, but the film quality was not good at deposition temperatures below 150 degrees C. The passviation quality was determined by measuring the effective carrier lifetime using the quasi-steady state photoconductance (QSS-PC) technique. Two, 5, 7.5 and 10 nm thick films were deposited at 150 degrees C and annealed at 200 degrees C for 1 hour. The carrier lifetime of these films was approximately 3 times higher than that observed before annealing. A p a-SiC:H/i a-Si:H/n c-Si hetero-structure solar cell with a 7.8% efficiency and approximately 85% quantum efficiency (QE) was obtained by inserting an intrinsic a-Si:H thin film (5 nm) between the interfaces. These results highlight the potential applications of a passivation layer to heterojunction solar cells.

Electron-emission properties of titanium carbide-coated carbon nanotubes grown on a nano-sized tungsten tip

Thin films (< 30 nm) of titanium carbide (TiC) are coated on carbon nanotubes (CNTs), directly grown on nano-sized (~ 500 nm in diameter) conical-type tungsten (W) tips, by employing an inductively coupled plasma chemical vapor deposition (ICP-CVD) technique. Modifications to structural properties (such as length to diameter ratio, crystal quality, and growth behavior) of CNTs due to TiC-coating are monitored using high-resolution TEM, field-emission SEM, and Raman spectroscopy. The driving voltage required to obtain the same level of emission current in CNTs-emitter is significantly reduced by TiC-coating. It is also noted that the degradation of emission current due to prolonged operation (up to 30 h) is remarkably suppressed by TiC-coating.

Characterization of MONOS nonvolatile memory by solid phase crystallization on glass

Solid phase crystallization (SPC) is carried out because of the best uniformity among the various crystallization methods. SPC poly-Si nonvolatile memory (NVM) is expected superior memory property in terms of stable reliability. This paper presents electrical properties of SPC poly-Si NVM on glass.Nonvolatile memory is an ideal portable storage device due to its characteristics of low-power consumption and compact size. Metal/oxide/nitride/oxide/silicon (MONOS) structure memory was fabricated on glass. Silicon oxynitride (SiOxNy) layer grown by nitrous oxide plasma served as a carrier tunnel layer, silicon nitride (SiNx) as charge trap region and silicon dioxide (SiO2) for blocking oxide were deposited to fabricate NVM on SPC poly-Si. SiOxNy, SiNx, and SiO2 films were deposited by using inductively coupled plasma chemical vapor deposition (ICP-CVD). Electrical properties of NVM on glass were analyzed gate voltage–drain current (VG–ID) and charge retention property. We obtained the NVM device with the programming voltage of −12 V, erasing of 11 V, and fast programming/erasing (P/E) time of 1 ms. It has a threshold voltage window memory of about 3.7 V and it still keep a wide threshold voltage window of 2.3 V after 10 years.

Interface structure of microcrystalline silicon deposited by inductive coupled plasma using internal low inductance antenna

Hydrogenated microcrystalline silicon (µc-Si:H) films were prepared by inductive coupled plasma chemical vapor deposition (ICP-CVD) system using internal low inductance antenna (LIA) units on various under layer composed of Si, O, and N. The resultant changes in the crystallinity of the µc-Si:H films were investigated using Raman scattering spectroscopy and the details of the interface structure were observed by high resolution transmission electron microscope. We had found that µc-Si:H film on the SiNx layer treated by O2 plasma has good interface quality. The highly crystallized µc-Si:H films with no amorphous incubation layer at interface of Si/SiNx could be directly deposited on the SiNx layer.

ICP-CVD 비정질 실리콘에 형성된 처리온도에 따른 저온 니켈실리사이드의 물성 변화

ICP-CVD(inductively-coupled Plasma chemical vapor deposition)를 사용하여 $250^{\circ}C$ 기판온도에서 140 nm 두께의 수소화된 비정질 실리콘( ${\alpha}$ -Si:H)을 제조하였다. 그 위에 30 nm-Ni을 열증착기를 이용하여 성막하고, $200{\sim}500^{\circ}C$ 사이에서 $50^{\circ}C$ 간격으로 30분간 진공열처리하여 실리사이드화 처리하였다. 완성된 실리사이드의 처리온도에 따른 실리사이드의 면저항값 변화, 미세구조, 상 분석, 표면조도 변화를 각각 사점면저항측정기, HRXRD(high resolution X-ray diffraction), FE-SEM(field emission scanning electron microscope), TEM(transmission electron microscope), SPM(scanning probe microscope)을 활용하여 확인하였다. $300^{\circ}C$ 에는 고저항상인 $Ni_3Si$ , $400^{\circ}C$ 에서는 중저항상인 $Ni_2Si$ , $450^{\circ}C$ 이상에서 저저항의 나노급 두께의 균일한 NiSi를 확인되었다. SPM결과에서 저저항 상인 NiSi는 $450^{\circ}C$ 에서 RMS(root mean square) 표면조도 값도 12 nm이하로 전체 공정온도를 $450^{\circ}C$ 까지 낮추어 유리와 폴리머기판 등 저온기판에 대응하는 저온 니켈모노실리사이드 공정이 가능하였다. 【We fabricated hydrogenated amorphous silicon(a-Si:H) 140 nm thick film on a $180\;nm-SiO_2/Si$ substrate with an inductively-coupled plasma chemical vapor deposition(ICP-CVD) equipment at $250^{\circ}C$ . Moreover, 30 nm-Ni film was deposited with a thermal-evaporator sequently. Then the film stack was annealed to induce silicides by a rapid thermal annealer(RTA) at $200{\sim}500^{\circ}C$ in every $50^{\circ}C$ for 30 minuets. We employed a four-point tester, high resolution X-ray diffraction(HRXRD), field emission scanning electron microscope(FE-SEM), transmission electron microscope(TEM), and scanning probe microscope(SPM) in order to examine the sheet resistance, phase transformation, in-plane microstructure, cross-sectional microstructure evolution, and surface roughness, respectively. We confirmed that nano-thick high resistive $Ni_3Si$ , mid-resistive $Ni_2Si$ , and low resistive NiSi phases were stable at the temperature of $350{\sim}450^{\circ}C$ , and > $450^{\circ}C$ , respectively. Through SPM analysis, we confirmed the surface roughness of nickel silicide was below 12 nm, which implied that it was superior over employing the glass and polymer substrates.】

Properties of Ge Films Grown Through Inductively Coupled Plasma Chemical Vapor Deposition on SiO2 Substrates

In this study, we investigated the physical and electrical characteristics of Ge polycrystalline films deposited directly onto -covered substrates using inductively coupled plasma chemical vapor deposition (ICP-CVD). The pure Ge films that we deposited at a relatively low temperature of exhibited the same cubic structure, with primarily (111), (220), and (311) orientations identified from X-ray diffraction patterns, as those deposited at . The use of such a low temperature not only prevented the plasma window of the chamber from overheating but also allowed crack-free, thicker films to be deposited more easily. The ability to deposit Ge films on was closely linked to the hydrogen etching effect, as evidenced by the results obtained using X-ray photoelectron spectroscopy. Although the crystalline characteristics of the low-temperature as-deposited Ge films were somewhat poorer than those obtained at , subsequent furnace annealing and rapid thermal annealing with a capping layer improved the crystalline quality significantly. These results, taken together with studies of the surface morphologies and dopant activation of the recrystallized Ge films, suggest that ICP-CVD might be a simple, powerful and reliable approach for the fabrication of polycrystalline Ge thin film transistors.

Study on the low leakage current of an MIS structure fabricated by ICP-CVD

As the dimensions of electric devices continue to shrink, it is becoming increasingly important to understand how to obtain good quality gate oxide film materials wilth higher carrier mobility, lower leakage current and greater reliability. All of them have become major concerns in the fabrication of thin film oxide transistors. A novel film deposition method called Inductively Coupled Plasma-Chemical Vapor Deposition (ICP-CVD) has received attraction in the semiconductor industry, because it can be capable of generating high density plasmas at extremely low temperature, resulting in less ion bombardment of the material surface. In this work, we present the results of crystallized silicon dioxide films deposited by inductively coupled plasma chemical vapor deposition technique at an extremely low temperature of 90°C. The value of the refractive index of the crystallized ICP-CVD SiO2 film depends on the r.f. power of the ICP system, and approximates to be 1.46. This value is comparable to that of SiO2 films prepared by thermal oxidation. As the r.f. power of ICP applied more than 1250 Watts, still only the (111) diffraction peak is observed by XRD, which implies a very strong preferred orientation or single crystal structure. Too low or too high r.f. power both produces amorphous SiO2 films. From the I-V curve, the MIS device with a SiO2 dielectric film has a lower leakage current density of 6.8×10-8A/cm2 at 1V as the film prepared at 1750 watts. The highest breakdown field in this study is 15.8 MV/cm. From the FTIR analysis, it was found that more hydrogen atoms incorporate into films and form Si-OH bonds as the r.f. power increases. The existence of Si-OH bonds leads to a poor reliability of the MIS device.

Electrical Properties of Boron and Phosphorus Doped μc-Si:H Films using Inductively Coupled Plasma Chemical Vapor Deposition Method for Solar Cell Applications

Hydrogenated microcrystalline silicon(<TEX>${\mu}c$</TEX>-Si:H) films were prepared using inductively coupled plasma chemical vapor deposition(ICP-CVD) method, electrical and optical properties of these films were studied as a function of silane concentration. And then, effect of <TEX>$PH_3\;and\;B_2H_6$</TEX> addition on their electrical properties was also investigated for solar cell application. Characterization of these films from X-ray diffraction revealed that the conductive film exists in microcrystalline phase embedded in an amorphous network. At <TEX>$PH_3/SiH_4$</TEX> gas ratio of <TEX>$0.9{\times}10^{-3}$</TEX>, dark conductivity has a maximum value of <TEX>${\sim}18.5S/cm$</TEX> and optical bandgap also a maximum value of <TEX>${\sim}2.39eV$</TEX>. Boron-doped <TEX>${\mu}c$</TEX>-Si:H films, satisfied with p-layer of solar cell, could be obtained at <TEX>${\sim}10^{-2}\;of\;B_2H_6/SiH_4$</TEX>.

High quality nanocrystalline silicon thin film fabricated by inductively coupled plasma chemical vapor deposition at 350 °C

High quality nanocrystalline silicon (nc-Si) film was deposited by inductively coupled plasma chemical vapor deposition (ICP-CVD) without substrate RF bias at 350°C. The nc-Si with a dense crystalline structure of the columnar type grew from the bottom to the top of the nc-Si film. A troublesome incubation layer did not exist at the bottom of the fabricated nc-Si film. A grain size of 40nm was measured by using a SEM image. When a RF bias of 100 and 200W was applied to the substrate to induce ion bombardment on the substrate, the crystalline structure and grains were not observed and a-Si deposition became dominant. The transition from nc-Si deposition into a-Si deposition can be attributed to ion bombardment which prevents nucleation and crystal growth at the surface of deposition. This shows that the reduction of ion bombardment can be a key factor to fabricate high quality nc-Si film. By using ICP-CVD with no substrate RF bias, ion bombardment can be reduced, while the density of plasma is kept high, so that high quality nc-Si can be fabricated due to the enhancement of crystalline growth on the surface.

A low damage Si3N4 sidewall spacer process for self-aligned sub-100 nm III–V MOSFETs

This paper investigates a low damage reactive ion etch (RIE) process to make thin silicon nitride sidewall spacers for the fabrication of self-aligned sub-100nm gate length III–V metal–oxide–semiconductor field-effect-transistors (MOSFETs). Self-alignment is essential to minimize the contribution to the parasitic series source/drain resistance (RSD) from the access region between the ohmic contact and the gate, whilst retaining the overall electrostatic integrity of the device. In this work, a blanket Si3N4 was deposited by room temperature inductively coupled plasma chemical vapour deposition (ICP-CVD) and etched by reactive ion etching in a SF6/N2 based chemistry. Conditions were optimised to ensure low damage to the underlying device layer stack. This process has successfully produced thin Si3N4 spacers for fabricating self-aligned GaAs MOSFETs. The sheet resistance of III–V MOSFET materials was monitored as a function of etch parameters to assess the impact of damage related effects on the electronic characteristics of the underlying material. The etching profile and the sheet resistance of the device layer structures were characterised by using scanning electronic microscope (SEM) and sonogage, respectively.

Low damage ashing and etching processes for ion implanted resist and Si3N4 removal by ICP and RIE methods

This paper presents a low damage, ion implantation mask removal process where the ion implantation mask, consisting of photoresist and Si3N4 deposited by room temperature ICP-CVD (inductively coupled plasma chemical vapour deposition), has been successfully removed through combining ICP (inductively coupled plasma) O2 plasma ashing and SF6/O2 reactive ion etching (RIE) of the Si3N4. The process leaves a clean, smooth post-etching surface with rms roughness of less than 1nm, on a device quality, high-κ GaxGdyOz (GGO) oxide layer for the fabrication of III–V metal-oxide-semiconductor field-effect-transistors (MOSFETs). Equally importantly, no etch induced damage occurs in the underlying high mobility III–V semiconductor layers. The post-etched GGO surface roughness and electrical transport properties of the underlying device layer structures were characterised by atomic force microscopy (AFM) and sonogage, respectively.