Indium Gallium Zinc Oxide Transistors Research Articles

A Comprehensive Guide to Fully Inkjet‐Printed IGZO Transistors

AbstractIn this concise review, the recent advancements in fully inkjet‐printed (IJP) indium‐gallium‐zinc‐oxide (IGZO) thin‐film transistors (TFTs) over the past years are discussed. IGZO has replaced hydrogenated amorphous silicon (a‐Si:H) as the primary channel material for liquid‐crystal display TFTs and has gained further attention due to the solution processability of IGZO inks. Despite the longstanding practice of printing IGZO for approximately fifteen years, the realization of fully inkjet‐printed devices, including both dielectric and electrode components, represents a recent milestone in research, potentially heralding a cost‐effective era for IGZO transistors. In this review, following an introductory exposition of IGZO, the focus is on the different ink formulations, currently deployed for solution‐processed IGZO devices, the intricacies of the printing procedure involved are delineated, and ongoing research endeavors pertaining to the printing of dielectrics and electrodes for such devices are expounded upon.

IGZO TFT Backplane Integration for µLED Flat-Panel Display

The focus of this work is the process integration of Indium Gallium Zinc Oxide (IGZO) transistors as a µLED backplane for row/column addressing. A single pixel is composed of a µLED driven by an arrangement of two transistors and a storage capacitor. The pixels are then arrayed on a glass substrate to support active-matrix control of monochrome and full color (RGB) displays from 1x1cm (50 x 50 pixels) up to 7.6 x 7.6 cm (380 x 380 pixels). Optimization of circuit parameters considering size and scan frequency was modeled using existing TFT and µLED electrical device compact models. New process parameters and procedures were determined for the proper integration of µLEDs in an existing TFT fabrication process. Red, green, and blue µLED devices were fabricated at Tyndall National Institute on native substrates and were transferred to TFT pixels using an X-Display MTP-1003 micro-transfer printer. The performance of individual test cells was assessed using an Agilent B1500, revealing a voltage transfer characteristic indicating the ability to modulate and control µLED current.

Improving bias stability of IGZO field-effect transistors through CF4 plasma treatment of Al2O3 dielectrics

In this study, the effects of the CF4 plasma treatment on the amorphous indium gallium zinc oxide (IGZO) material were explored. The electrical characteristics of the IGZO-based field-effect transistor (FET) were also thoroughly examined to analyze the influence of the plasma treatment. Excellent adhesion of the sol-gel-based IGZO semiconducting film was achieved owing to the strong dipole moment of the AlOxFy layer created by the surface treatment. In particular, X-ray photoelectron spectroscopy depth profiles and transmission electron microscopy electron energy loss spectroscopy analyses provided clear evidence that fluorine atoms diffused into the Al2O3 surface via the CF4 plasma treatment. The formation of an AlOxFy layer at the IGZO/Al2O3 interface is expected to be advantageous for reducing the interface trap density, thereby enhancing the critical transistor parameters. Additionally, the plasma-treated IGZO transistor demonstrated strong electrical bias stability under continuous gate bias stress conditions. Therefore, surface modification via CF4 plasma treatment is proposed to boost the stability and performance of the device, offering a straightforward approach for integrated thin-film transistor circuitry in advanced display applications.

Substrate temperature effects on PEALD HfAlO dielectric films for IGZO-TFT applications

Aluminum incorporated hafnium oxide (HfAlO) has garnered significant attention due to its high dielectric constant. The present study employs supercycle plasma-enhanced atomic layer deposition (PEALD) to prepare HfAlO films, switching between HfO2 and Al2O3 deposition. The effects of substate temperature on the HfAlO films are systematically investigated. The experimental results indicate that increased substrate temperatures favor Al2O3 growth on HfO2, but excessively high temperatures result in deviated PEALD growth and deteriorated film properties. The PEALD window can be reached at substrate temperatures of 300 to 350 °C. The Al content is substantially affected by the substrate temperature, despite a constant Al2O3 PEALD cycle ratio used. The film deposited at 350 °C exhibits the highest Al content, density, and (111) crystalline orientation ratio, leading to a high breakdown field of 6 MV/cm and a considerable dielectric constant of 27. The HfAlO films are applied to indium gallium zinc oxide transistor as the dielectric layer, and the 350 °C-deposited HfAlO leads to the best device performance with a remarkably high on/off current ratio of 3.5 × 109, low threshold voltage of −0.1 V, saturated mobility of 6.1 cm2 V−1 s−1, and a low subthreshold swing of 76 mV/dec.

A CsPbI3/PCBM Phototransistor with Low Dark Current by Suppressing Ion Migration

Perovskite-based metal oxide phototransistors have emerged as promising photodetection devices owing to the superior optoelectronic properties of perovskite materials and the high carrier mobility of metal oxides. However, high dark current has been one major problem for this type of device. Here, we studied the dark current behaviors of phototransistors fabricated based on the Indium Gallium Zinc Oxide (IGZO) channel and different perovskite materials. We found that depositing organic–inorganic hybrid perovskites materials (MAPbI3/FAPbI3/FA0.2MA0.8PbI3) on top of IGZO transistor can increase dark current from ~10−6 mA to 1~10 mA. By contrast, we observed depositing an inorganic perovskite material, CsPbI3, incorporated with PCBM additive can suppress the dark current down to ~10−6 mA. Our study of ion migration reveals that ion migration is pronounced in organic–inorganic perovskite films but is suppressed in CsPbI3, particularly in CsPbI3 mixed with PCBM additive. This study shows that ion migration suppression by the exclusion of organic halide and the incorporation of PCBM additive can benefit low dark current in perovskite phototransistors.

Reliability Engineering of High‐Mobility IGZO Transistors via Gate Insulator Heterostructures Grown by Atomic Layer Deposition

AbstractThe reliability of oxide‐semiconductor (OS) thin‐film transistors (TFTs) is significantly influenced by the gate insulator (GI). During electrical bias stress, the defect sites near the semiconductor/GI interface and/or within the GI may trap electrons, which makes the threshold voltage (Vth) shift toward positive values. On the other hand, carbon (C) or hydrogen (H) atoms may diffuse from the GI into the active layer, and act as shallow donors, which induce negative Vth shifts (ΔVth). In this paper, an in situ atomic layer deposition (ALD)‐based GI heterostructure is introduced, which consists of a stack of two complementary materials, namely Al2O3 and SiO2. Here, a competition occurs between electron trapping in Al2O3 (positive ΔVth) and carrier generation from H atoms in SiO2 (negative ΔVth) which allows the achievement of nearly zero ΔVth under positive bias temperature stress (PBTS). This strategy is successfully applied to a high‐mobility (>50 cm2 Vs−1) ALD‐based indium‐gallium‐zinc oxide (IGZO) device, resulting in a net ∆Vth of −0.02 V under PBTS and drain current variation (∆ID) of +0.49% under constant current stress (CCS). The application of an in situ ALD process thus offers valuable insights to resolve the mobility versus reliability trade‐off in high‐performance oxide TFTs.

Electrolyte-gated amorphous IGZO transistors with extended gates for prostate-specific antigen detection.

The prostate-specific antigen (PSA) test is considered an important way for preoperative diagnosis and accurate screening of prostate cancer. Current antigen detection methods, including radioimmunoassay, enzyme-linked immunosorbent assay and microfluidic electrochemical detection, feature expensive equipment, long testing time and poor stability. Here, we propose a portable biosensor composed of electrolyte-gated amorphous indium gallium zinc oxide (a-IGZO) transistors with an extended gate, which can achieve real-time, instant PSA detection at a low operating voltage (<2 V) owing to the liquid-free ionic conductive elastomer (ICE) serving as the gate dielectric. The electric double layer (EDL) capacitance in ICE enhances the accumulation of carriers in the IGZO channel, leading to strong gate modulation, which enables the IGZO transistor to have a small subthreshold swing (<0.5 V dec-1) and a high on-state current (∼4 × 10-4 A). The separate, biodegradable, and pluggable sensing pad, serving as an extended gate connected to the IGZO transistor, prevents contamination and depletion arising from direct contact with biomolecular buffers, enabling the IGZO transistor to maintain superior electronic performance for at least six months. The threshold voltage and channel current of the transistor exhibit excellent linear response to PSA molecule concentrations across five orders of magnitude ranging from 1 fg mL-1 to 10 pg mL-1, with a detection limit of 400 ag mL-1 and a detection time of ∼5.1 s. The fabricated biosensors offer a point-of-care system for antigen detection, attesting the feasibility of the electrolyte-gated transistors in clinical screening, healthcare diagnostics and biological management.

Nanowire-Enhanced Fully Transparent and Flexible Indium Gallium Zinc Oxide Transistors with Chitosan Hydrogel Gate Dielectric: A Pathway to Improved Synaptic Properties.

In this study, a transparent and flexible synaptic transistor was fabricated based on a random-network nanowire (NW) channel made of indium gallium zinc oxide. This device employs a biocompatible chitosan-based hydrogel as an electrolytic gate dielectric. The NW structure, with its high surface-to-volume ratio, facilitated a more effective modulation of the channel conductance induced by protonic-ion polarization. A comparative analysis of the synaptic properties of NW- and film-type devices revealed the distinctive features of the NW-type configuration. In particular, the NW-type synaptic transistors exhibited a significantly larger hysteresis window under identical gate-bias conditions. Notably, these transistors demonstrated enhanced paired-pulse facilitation properties, synaptic weight modulation, and transition from short- to long-term memory. The NW-type devices displayed gradual potentiation and depression of the channel conductance and thus achieved a broader dynamic range, improved linearity, and reduced power consumption compared with their film-type counterparts. Remarkably, the NW-type synaptic transistors exhibited impressive recognition accuracy outcomes in Modified National Institute of Standards and Technology pattern-recognition simulations. This characteristic enhances the efficiency of practical artificial intelligence (AI) processes. Consequently, the proposed NW-type synaptic transistor is expected to emerge as a superior candidate for use in high-efficiency artificial neural network systems, thus making it a promising technology for next-generation AI semiconductor applications.

High Performance and High Yield Solution Processed IGZO Thin Film Transistors Fabricated with Low‐Temperature Annealed Hafnium Dioxide Gate Dielectric

AbstractSolution‐processed microelectronics offer advantages, including cost‐effectiveness, higher energy efficiency, and compatibility with rapid prototyping compared to their counterparts fabricated through traditional semiconductor manufacturing processes. Unfortunately, solution‐processed transistors exhibit wide performance variability and low yield. In this work, a solution‐processed transparent indium gallium zinc oxide (IGZO) thin film transistor with a low temperature‐annealed hafnium oxide dielectric layer is described. Post‐annealing temperatures for the sol–gel hafnium dioxide thin film are reduced to below 200 °C, significantly expanding the range of substrates on which the metal oxide dielectric can be deposited. The fabricated devices exhibit excellent characteristics with high field‐effect mobilities of over 85 cm2 V−1 s−1, along with low subthreshold swing below 140 mV dec−1, high on/off ratios, and near‐zero threshold voltages when operating stably at low‐operating voltages of 2 V. The solution processed transparent hafnium dioxide gate dielectric IGZO transistors are shown to exhibit comparatively significantly lower device variation and high yield, allowing for the reproducible fabrication of large‐area and transparent solution processed microelectronics systems.

Approaches for 3D Integration Using Plasma-Enhanced Atomic-Layer-Deposited Atomically-Ordered InGaZnO Transistors with Ultra-High Mobility.

As the scale-down and power-saving of silicon-based channel materials approach the limit, oxide semiconductors are being actively researched for applications in 3D back-end-of-line integration. For these applications, it is necessary to develop stable oxide semiconductors with electrical properties similar to those of Si. Herein, a single-crystal-like indium-gallium-zinc-oxide (IGZO) layer (referred to as a pseudo-single-crystal) is synthesized using plasma-enhanced atomic layer deposition and fabricated stable IGZO transistors with an ultra-high mobility of over 100cm2 Vs-1 . To acquire high-quality atomic layer deposition-processed IGZO layers, the plasma power of the reactant is controlled as an effective processing parameter by evaluating and understanding the effect of the chemical reaction of the precursors on the behavior of the residual hydrogen, carbon, and oxygen in the as-deposited films. Based on these insights, this study found that there is a critical relationship between the optimal plasma reaction energy, superior electrical performance, and device stability.

Solution processed rare-earth doped high-k dielectrics for low-power IGZO transistors

Low-power metal oxide transistors are highly required in displays, logic circuit and sensors. High quality gate dielectrics with the properties of high dielectric constant, smooth surface, and excellent insulating performance are critical to realize the above mentioned transistors. In this work, we present a universal strategy by using rare-earth (RE) elements (Y, Er and Yb) as dopants to improve the dielectric properties of zirconia film for low-power transistors. Additionally, all the dielectric films are prepared by solution process, which is compatible with low-cost and large-area manufacturing technology. The leakage current densities of zirconia films decrease from 1.27 × 10−5 A/cm2 to 2.8 × 10−7 A/cm2, 6.6 × 10 − 7 A/cm2, and 4.3 × 10−7 A/cm2 by doping a small amount of Y, Er, and Yb in zirconia films, respectively. Furthermore, bottom-gate top-contact indium-gallium-zinc oxide (IGZO) transistors with RE-doped zirconia dielectrics show one order improved current on/off (∼104) ratio and achieve one order improvement in mobility (3.11, 2.85, 2.75 cm2V−1S−1 for Y-, Er-, Yb-doped devices respectively) compared with that of pure zirconia film based devices (0.30 cm2V−1S−1). Moreover, the subthreshold swing (SS) of TFTs based on RE-doped and undoped ZrO2 dielectric films are calculated (0.2, 0.36, 0.21 V/dec for Y-, Er-, Yb-doped devices respectively, and 0.51 V/dec for undoped devices) This study demonstrates the validity of RE ions as dopants in gate dielectrics to achieve high-performance low-power metal oxide transistors.

Thermal shape morphing of membrane-type electronics based on plastic-elastomer frameworks for 3D electronics with various Gaussian curvatures

This study demonstrates a means of shape morphing planar membrane-type electronic devices into three-dimensional (3D) structures with various Gaussian curvatures using a plastic-elastomer supportive framework consisting of acrylonitrile–butadienestyrene (ABS) lines with tensile stress inside an Ecoflex film. The plastic part, created by extrusion shear printing (ESP), provides the driving force for shape morphing upon thermal annealing, whereas the elastomer part provides a base to mount membrane-type electronic devices and allows a comparably large degree of deformation. To ensure reliable interfacial adhesion in the plastic-elastomer framework, the ABS lines are treated with an allyl-terminated self-assembled monolayer (SAM) for chemical bonding to the Ecoflex layer. To determine control parameters for reliable shape morphing, the annealing conditions (e.g., temperature and time), the printing conditions (e.g., shear rate and pitch), and relative thicknesses of the ABS/Ecoflex are examined. Based on these findings, various 3D structures, including bent, cone, saddle, and dome shapes, can be generated from planar forms using ABS-Ecoflex frameworks, which are also predicted by a mechanical finite element method (FEM) simulation. Furthermore, a metal electrode and a membrane-type indium gallium zinc oxide (IGZO) transistor array are successfully mounted on ABS-Ecoflex frameworks and transformed into curvilinear structures without electrical failure.

Beol-Compatible Ingazno-Based Devices for 3D Integrated Circuits

Due to its attractive materials and electrical properties, indium-gallium-zinc-oxide (IGZO) has been extensively researched in many emerging technologies, especially for three-dimensional (3D) monolithic integration and back-end-of-line (BEOL) compatible applications [1]. On the pathway toward the realization of high-performance 3D monolithic integrated chips (ICs), a wide range of building blocks with different functionalities are required. 3D monolithic ICs also demand optimization in device performance and circuit architecture design.In this paper, we discuss our recent research development in IGZO-based techniques at both device and circuit levels. This includes nanowire structure for IGZO-based transistors, as well as the BEOL-compatible ferroelectric ternary content-addressable memory (TCAM) and embedded dynamic random-access-memory (eDRAM) for compute-in-memory (CiM) using IGZO-based transistors.A novel digital etch technique for amorphous IGZO (α-IGZO) material as well as the formation of α-IGZO nanowires were realized, enabling high performance α-IGZO nanowire field-effect transistors (NWFETs) with ultra-scaled nanowire width (W NW) [2]. The scanning electron microscopy (SEM) images of α-IGZO nanowire before and after the digital etch show that the nanowire structure as well as W NW reduction after digital etch can be clearly observed. The smallest α-IGZO nanowire after digital etch has a W NW of ~20 nm. By leveraging the ultra-scaled nanowire structure, the NWFET with the smallest W NW achieves decent subthreshold swing of 80 mV/decade as well as high peak extrinsic transconductance (G m,ext) of 612 μS/μm at a drain to source voltage (V DS) = 2 V (456 μS/μm at V DS = 1 V). As compared with previous works in literature, our IGZO NWFET achieves one of the highest peak G m among all IGZO-based FETs. α-IGZO ferroelectric FETs (Fe-FETs) with a metal-ferroelectric-metal-oxide-semiconductor (MFMIS) structure were further realized based on the α-IGZO transistor process modules. The smallest L CH is as small as 40 nm. The cross-sectional transmission electron microscopy (TEM) image of the device shows sharp interface. The α-IGZO Fe-FETs achieve a large memory window of 2.9 V, high endurance of 108 cycles, high conductance ratio, and small cycle-to-cycle variation. By leveraging the low temperature processed α-IGZO Fe-FETs with good electrical characteristics, a BEOL-compatible ferroelectric TCAM circuit with 2 Fe-FETs connected in parallel was realized [3], showing an extremely large sensing margin. In addition, such α-IGZO Fe-FET TCAM reduces the transistor number from 16 to 2 as compared to traditional SRAM-based TCAM. Smaller cell size and higher energy efficiency can also be obtained.IGZO transistors can play an important role in in-memory computing as well. SEM image of the eDRAM CiM cell shows utilization of IGZO transistors. The smallest device has L CH of 45 nm [4]. The IGZO transistor-based eDRAM CiM with differential cell structure achieves low leakage current, low variation, low charge loss sensitivity, and the control-friendly charge-domain computing without DC power. By evaluating the key figure-of-merits, including precision, power efficiency, computing density, retention time, and robustness, it can be concluded that our IGZO transistor-based eDRAM CiM is promising for low-power and scalable compute-in-eDRAM design. Acknowledgments: This work is supported by Singapore Ministry of Education (Tier 2: MOE2018-T2-2-154, Tier 1: R-263-000-D65-114).

Hysteresis and turn-on voltage tailoring of indium gallium zinc oxide transistors by employing a sandwiched structure with indium oxide

• Transistor with ternary oxide semiconductor shows large hysteresis at low voltage. • Hysteresis can be addressed by improving semiconductor-dielectric interface. • Forming a sandwich structure with In 2 O 3 reduces hysteresis. • Turn-on voltage of transistors is controlled via the In 2 O 3 film thickness. Transparent electronics with low power consumption is an important area of research for the display industry. Operating voltages of transistors can be successfully reduced by employing gate dielectrics with high dielectric constants. However, interfacial trap sites between dielectric and semiconductor layers might cause hysteresis. Here, transistors were fabricated using amorphous indium gallium zinc oxide (a-IGZO, molar ratio of In:Ga:Zn 1:1:1), a transparent semiconductor with high electron mobility. When prepared on top of Al 2 O 3 gate dielectric, drain current was found to depend on the direction of the gate sweep. A stacked active layer was prepared with the a-IGZO being sandwiched between In 2 O 3 thin films to mitigate the hysteresis of the device. Moreover, it was found that by varying the In 2 O 3 layer thickness, the device fabrication can be optimized to improve the device-to-device reproducibility of the charge carrier mobility. Additionally, the turn-on voltage, a crucial parameter of transistors in binary logic circuits, improved significantly when using the optimized layer structure.

Monolithic Integration of Perovskite Photoabsorbers with IGZO Thin‐Film Transistor Backplane for Phototransistor‐Based Image Sensor

AbstractMonolithic integration of perovskite materials and their optoelectronic devices with well‐developed thin‐film transistor (TFT) backplane is leading to new applications in displays and image sensors. Herein, a scalable polyimide assisted patterning approach for monolithic integration of perovskite based high‐sensitive phototransistor array on indium gallium zinc oxide (IGZO) active matrix backplane is introduced. Polyimide vias are first formed by conventional photolithography process, through which uniform perovskite films of arbitrary patterns with feature size less than 20 µm are fabricated by spin‐on‐patterning method. Using this technique, patterns of quasi 2D perovskite photoabsorbing layer are precisely deposited onto the channel area of the photosensing IGZO TFT, forming high‐performance phototransistors with responsivity and detectivity reaching 835.7 A W−1 and 5.4 × 1012 Jones, respectively. An image sensor with 8 × 8 pixels array containing both photosensing perovskite/IGZO transistors and switching IGZO transistors is demonstrated, in which the switching IGZO transistor elements on the backplane are protected by the non‐patterned region of the polyimide encapsulation layer. This whole fabrication process is compatible with TFT manufacturing process and will significantly reduce the cost needed for constructing next generation high‐resolution image sensors.

Impact of electrode materials on the performance of amorphous IGZO thin-film transistors

This study reports on the fabrication and characterization of thin-film transistors (TFTs) based on indium–gallium–zinc–oxide (IGZO) with various source- and drain-region metals (Pt, W and Ti). The performance of the IGZO transistors is compared to TFTs based on hydrogenated amorphous silicon (a-Si:H) with Pt source- and drain-regions. From the output characteristics maximum saturation mobilities of µ = 0.45 cm2/Vs for a-Si:H, and µ = 24 to 50 cm2/Vs for IGZO TFTs are extracted, which are competitive to high-performance thin-film transistors. The study reveals a general influence of the source- and drain-electrode material on the maximum saturation mobility and inverse sub-threshold slope.Graphical abstract

High-performance inorganic metal halide perovskite transistors

The p-type characteristic of solution-processed metal halide perovskite transistors means that they could be used in combination with their n-type counterparts, such as indium–gallium–zinc-oxide transistors, to create complementary metal–oxide–semiconductor-like circuits. However, the performance and stability of perovskite-based transistors do not yet match their n-type counterparts, which limit their broader application. Here we report high-performance p-channel perovskite thin-film transistors based on inorganic caesium tin triiodide semiconducting layers that have moderate hole concentrations and high Hall mobilities. The perovskite channels are formed by engineering the film composition and crystallization process using a tin-fluoride-modified caesium-iodide-rich precursor with lead substitution. The optimized transistors exhibit field-effect hole mobilities of over 50 cm2 V−1 s−1 and on/off current ratios exceeding 108, as well as high operational stability and reproducibility.

A thin and flexible scanner for fingerprints and documents based on metal halide perovskites

Solution-processed photodetectors could be of use in large-area light-sensing applications because they can be fabricated at low cost on plastic substrates and their absorption spectra can be tuned by chemical design. However, fabricating photodetectors with low dark currents and integrating them into high-resolution backplanes remains challenging. Here we show that solution-processed metal halide perovskite photodiodes on top of an amorphous indium gallium zinc oxide transistor backplane can be used to create a flexible image sensor that is ~100 μm thick and has a resolution of 508 pixels per inch. We have developed a pixel edge cover layer for the system that reduces electrode current leakage and thus dark current density. The low noise current in combination with high external quantum efficiency results in high photodetectivity at wavelengths from 550 nm to 770 nm. We show that our imager can be used for document scanning and biometric fingerprinting and that it can be wrapped around objects with radii as small as 0.6 cm. Low-dark-current perovskite photodetectors can be integrated with an oxide transistor backplane to create a high-resolution optical scanning array capable of imaging flat and curved surfaces.

Construction of high stability indium gallium zinc oxide transistor biosensors for reliable detection of bladder cancer-associated microRNA

Bladder cancer is the most common malignant tumours with high morbidity, mortality and recurrence. However, currently developed detection methods for bladder cancer-associated urine biomarkers are hindered by their extremely low abundance. Hence, the exploration of a highly sensitive and selective approach for the detection of trace bladder cancer-associated biomarkers in human urine is of vital importance for the diagnosis of bladder cancer. Herein, we developed a highly reliable indium gallium zinc oxide field effect transistor (IGZO FET) biosensor for the detection of bladder cancer-related biomarker microRNA. The single-stranded DNA-functionalized IGZO FET biosensors exhibit high sensing reproducibility and stability with an ultralow detection limit of 19.8 amol/L. The device could also be used for quantitative detection of trace microRNA in human urine samples and can effectively distinguish bladder cancer patients from healthy donors. The development of high performance IGZO FET biosensors presents new opportunities for the achievement of early-stage diagnosis of bladder cancer.

Reliability-Aware SPICE Compatible Compact Modeling of IGZO Inverters on a Flexible Substrate

Accurate circuit simulation reflecting physical and electrical stress is of importance in indium gallium zinc oxide (IGZO)-based flexible electronics. In particular, appropriate modeling of threshold voltage (VT) changes in different bias and bending conditions is required for reliability-aware simulation in both device and circuit levels. Here, we present SPICE compatible compact modeling of IGZO transistors and inverters having an atomic layer deposition (ALD) Al2O3 gate insulator on a polyethylene terephthalate (PET) substrate. Specifically, the modeling was performed to predict the behavior of the circuit using stretched exponential function (SEF) in a bending radius of 10 mm and operating voltages ranging between 4 and 8 V. The simulation results of the IGZO circuits matched well with the measured values in various operating conditions. It is expected that the proposed method can be applied to process improvement or circuit design by predicting the direct current (DC) and alternating current (AC) responses of flexible IGZO circuits.