Indium Gallium Zinc Oxide Transistors Research Articles

Electromechanical properties of amorphous indium–gallium–zinc-oxide transistors structured with an island configuration on plastic

A comparative study of the electromechanical properties was carried out on a low-temperature-processed amorphous indium–gallium–zinc-oxide thin-film transistor, particularly with regard to the structural design of the device under the stress accumulation of an outward bending surface. Shown herein is the reliable electromechanical integrity of island-structured devices against the mechanical strain at bending radii of mm order. The onset of crack strain also closely corresponded to the electrical failure of the stressed device. These results revealed that the island configuration on the bending surface effectively suppresses the stress accumulation on sheets composed of inorganic stacked layers in a uniaxial direction.

Highly bendable characteristics of amorphous indium–gallium–zinc-oxide transistors embedded in a neutral plane

The electromechanical response of an amorphous indium–gallium–zinc-oxide (a-IGZO) thin-film transistor (TFT) fabricated on a polyimide substrate was investigated as a function of the neutral axis location and strain history of the bending system. Here, we demonstrate the pronounced bending characteristics of a-IGZO TFTs and their backplane under extreme mechanical strain when they are embedded in a neutral plane (NP). After being subjected to tensile stress, the devices positioned near the NP were observed to function well against a cyclic bending stress of 2 mm radius with 100,000 times, while TFTs farther from the neutral surface exhibited modified electrical properties.

Fourier spectrum based extraction of an equivalent trap state density in indium gallium zinc oxide transistors

Segregating the dynamics of gate bias induced threshold voltage shift, and in particular, charge trapping in thin film transistors (TFTs) based on time constants provides insight into the different mechanisms underlying TFTs instability. In this Letter we develop a representation of the time constants and model the magnitude of charge trapped in the form of an equivalent density of created trap states. This representation is extracted from the Fourier spectrum of the dynamics of charge trapping. Using amorphous In-Ga-Zn-O TFTs as an example, the charge trapping was modeled within an energy range of ΔEt≈ 0.3 eV and with a density of state distribution as Dt(Et−j)=Dt0exp(−ΔEt/kT)with Dt0 = 5.02 × 1011 cm−2 eV−1. Such a model is useful for developing simulation tools for circuit design.

State retention flip flop architectures with different tradeoffs using crystalline indium gallium zinc oxide transistors implemented in a 32-bit normally-off microprocessor

As leakage power continues to increase when transistor sizes are downscaled, it becomes increasingly hard to achieve low power consumption in modern chips. Normally-off processors use state-retention and non-volatile circuits to make power gating more efficient with less static power. In this paper, we propose two novel state-retention flip-flop designs based on a parallel and series retention circuit architectures utilizing crystalline indium gallium zinc oxide transistors, which can achieve state retention with zero static power. To demonstrate the application of these different designs, they are implemented in a 32-bit normally-off microprocessor with an energy break-even time of 1.47 µs for the parallel type design and 0.93 µs for the series type design, at a clock frequency of 15 MHz. We show that decreasing the power supply duty cycle to 0.9%, the average current of the processor core can be decreased by over 99% using either type of flip-flop.

A normally-off microcontroller unit with an 85% power overhead reduction based on crystalline indium gallium zinc oxide field effect transistors

A low-power normally-off microcontroller unit (NMCU) having state-retention flip-flops (SRFFs) using a c-axis aligned crystalline oxide semiconductor (CAAC-OS) such as indium gallium zinc oxide (IGZO) transistors and employing a distributed backup and recovery method (distributed method) is fabricated. Compared to an NMCU employing a centralized backup and recovery method (centralized method), the NMCU employing the distributed method can be powered off approximately 75 µs earlier after main processing and can start the main processing approximately 75 µs earlier after power-on. The NMCU employing the distributed method can reduce power overhead by approximately 85% and power consumption by approximately 18% compared to the NMCU employing the centralized method. The NMCU employing the distributed method can retain data even when it is powered off, can back up data at high speed, and can start effective processing immediately after power-on. The NMCU could be applied to a low-power MCU.

Electrical characteristics and short-channel effect of c-axis aligned crystal indium gallium zinc oxide transistor with short channel length

A channel length of a c-axis aligned crystal indium gallium zinc oxide (CAAC-IGZO) transistor having low off-state current at a yA/µm level was decreased to 100 nm, and the electrical characteristics and short-channel effect of the CAAC-IGZO transistor were researched. As a result, we found that, in the CAAC-IGZO transistor with L = 100 nm, even with a gate insulator film having an equivalent oxide thickness (EOT) = 11 nm, an extremely small off-state current of 380 yA/µm at 85 °C is maintained, in addition channel length dependence of the electrical characteristics is hardly seen. Favorable values of characteristics of the CAAC-IGZO transistor can be obtained, such as subthreshold slope (SS) = 77 mV/dec, drain induced barrier lowering (DIBL) = 73 mV/V, threshold voltage (Vth) = 0.65 V, and on-state current (Ion) = 65 µA/µm. These results suggest the possibility that the CAAC-IGZO transistor can be applied to an LSI in a deep submicron region.

Low turn-on voltage due to conduction band lowering effect in crystalline indium gallium zinc oxide transistors

We found out that in an indium gallium zinc oxide (IGZO) transistor, the energy barrier in the channel region, i.e., the conduction band energy relative to the Fermi energy is lowered by electrons flowing from n+ regions under source and drain electrodes. We have named this phenomenon “conduction band lowering (CBL) effect”. Owing to this effect, even when the Fermi energy of an IGZO film gets closer to the mid-gap, a transistor formed using the film in the channel region is always turned on around a gate voltage of 0 V. In other words, by sufficiently reducing the donor concentration of the channel region, such IGZO transistors are turned on at a certain low gate voltage determined by the CBL effect and their characteristics variation can be suppressed.

Solution processed amorphous InGaZnO semiconductor thin films and transistors

Amorphous indium gallium zinc oxide (a-IGZO) semiconductor thin films and transistors were deposited on alkali-free glasses by the sol–gel route. The atomic ratio of In:Ga:Zn in the solution was 0.7:0.3:1. In this study, the effects of annealing temperature on the structural, surface condition, optical transmittance, and electrical resistivity of a-IGZO semiconductor thin films were investigated. GIXRD measurements and TEM-NBD analysis indicated that all annealed IGZO thin films had an amorphous phase structure. The dried IGZO sol–gel films annealed at a temperature higher than 425°C had a flat surface and exhibited high transparency (>89%) in the visible region. According to results from TGA, FT-IR and XPS, the residual organic compounds in the dried IGZO sol–gel films were completely removed at the annealing temperatures higher than 450°C. Therefore, we chose the 450°C annealed thin film as the active channel layer in the bottom-gate, bottom-contact (BGBC) thin-film transistor (TFT) in the present study. Current–voltage (I–V) characteristics of the 450°C annealed a-IGZO TFT revealed that it operated in n-type behavior with a positive threshold voltage (enhancement mode).

In–Ga–Zn–O thin film transistor with HfO2 gate insulator prepared using various O2/(Ar + O2) gas ratios

We have investigated the effect of the deposition of an HfO2 thin film as a gate insulator with different O2/(Ar+O2) gas ratios using RF magnetron sputtering. The HfO2 thin film affected the device performance of amorphous indium–gallium–zinc oxide transistors. The performance of the fabricated transistors improved monotonously with increasing O2/(Ar+O2) gas ratio: at a ratio of 0.35, the field effect mobility of the amorphous InGaZnO thin film transistors was improved to 7.54cm2/(Vs). Compared to those prepared with an O2/(Ar+O2) gas ratio of 0.05, the field effect mobility of the amorphous InGaZnO thin film transistors was increased to 1.64cm2/(Vs) at a ratio of 0.35. This enhancement in the field effect mobility was attributed to the reduction of the root mean square roughness of the gate insulator layer, which might result from the trap states and surface scattering of the gate insulator layer at the lower O2/(Ar+O2) gas ratio.

Reduced Contact Resistance in Inkjet Printed High-Performance Amorphous Indium Gallium Zinc Oxide Transistors

Solution processing of amorphous metal oxide materials to fabricate thin-film transistors (TFTs) has received great recent interest. We demonstrate here an optimized "ink" and printing process for inkjet patterning of amorphous indium gallium zinc oxide (a-IGZO) TFTs and investigate the effects of device structure on derived electron mobility. Bottom-gate top-contact (BGTC) TFTs are fabricated and shown to exhibit electron mobilities comparable to a-Si:H. Furthermore, a record electron mobility of 2.5 cm(2) V(-1) s(-1) is demonstrated for bottom-gate bottom-contact (BGBC) TFTs. The mechanism underlying such impressive performance is investigated using transmission line techniques, and it is shown that the semiconductor-source/drain electrode interface contact resistance is nearly an order of magnitude lower for BGBC transistors versus BGTC devices.

Evaluation of Off-State Current Characteristics of Transistor Using Oxide Semiconductor Material, Indium–Gallium–Zinc Oxide

We measured a significantly low off-state current (135 yA/µm at 85 °C) of a metal oxide semiconductor (MOS) transistor using indium–gallium–zinc oxide (IGZO), which is an oxide semiconductor material. Note that “y” is 10-24. A transistor in which the hydrogen concentration in an IGZO film is lowered (5×1019 cm-3 or lower) was used. To estimate the minute current accurately, we established a measurement method in which changes in the amount of electrical charge are measured for a long time. Such extremely low off-state current characteristics show promise for new applications of IGZO transistors in memories.

Zirconium oxide-aluminum oxide nanolaminate gate dielectrics for amorphous oxide semiconductor thin-film transistors

The dielectric properties of ZrO2–Al2O3 nanolaminates, deposited via atomic layer deposition, and their impact on the performance and stability of indium gallium zinc oxide and zinc tin oxide amorphous oxide semiconductor thin-film transistors (TFTs) are investigated. It is found that nanolaminate dielectrics can combine the advantages of constituent dielectrics and produce TFTs with improved performance and stability compared to single layer gate dielectrics. It is also found that TFT performance and stability are influenced not only by the chemical composition of the gate dielectric/channel interface but also by the thickness and composition of the laminate layers in the dielectric near the interface.

The influence of visible light on the gate bias instability of In–Ga–Zn–O thin film transistors

We investigated the effect of photon irradiation with various energies on the gate bias instability of indium–gallium–zinc oxide transistors. The illumination of red and green light on the transistor caused positive threshold voltage ( V th) shifts of 0.23 V and 0.18 V, respectively, while it did not affect the V th value in blue light after a positive bias stress. However, the stability of transistors was deteriorated with increasing photon energy after a negative bias stress: negative V th shifts for red (−0.23 V) and blue light (−3.7 V). This difference can be explained by the compensation effect of the electron carrier trapping and the creation of meta-stable donors via photon excitation.

Transparent indium gallium zinc oxide transistor based floating gate memory with platinum nanoparticles in the gate dielectric

A transparent memory device has been developed based on an indium gallium zinc oxide thin film transistor by incorporating platinum nanoparticles in the gate dielectric stack as the charge storage medium. The transfer characteristics of the device show a large clockwise hysteresis due to electron trapping and are attributed to the platinum nanoparticles. Effect of the gate bias stress (program voltage) magnitude, duration, and polarity on the memory window characteristics has been studied. Charge retention measurements were carried out and a loss of less than 25% of the trapped elec-trons was observed over 104 s indicating promising application as nonvolatile memory.

Impact of high-k TiOx dielectric on device performance of indium-gallium-zinc oxide transistors

We investigated the effect of the high-k TiOx (k∼40) gate dielectric on the mobility (μFE) of indium-gallium-zinc oxide (IGZO) transistors. As the thickness of the TiOx layer at the interface of the IGZO channel and SiNx gate dielectric layer increased from 2 to 8 nm, the μFE value was monotonously reduced from 9.9 to 1.8 cm2/V s. The degradation of the mobility was attributed to the Coulomb scattering mechanism rather than the phonon scattering mechanism of the high-k TiOx layer based on the behavior of the temperature-dependent mobilities for all of the IGZO transistors.

Organic/inorganic hybrid complementary circuits based on pentacene and amorphous indium gallium zinc oxide transistors

Complementary inverters composed of pentacene for the p-channel thin-film transistors (TFTs) and amorphous indium gallium zinc oxide for the n-channel TFTs have been fabricated on glass substrates. The p- and n-channel TFTs have field-effect mobilities of 0.6 and 17.1 cm2/V s, respectively, and inverters yield a high gain of ∼56. Complementary five-stage ring oscillator exhibits a good dynamic operation with an output frequency of 200 Hz at 10 V. Since both channel layers are stable in air and can be formed by room temperature deposition process, the hybrid circuits are applicable to flexible electronic devices.

Control of threshold voltage in ZnO-based oxide thin film transistors

We investigated the feasibility of controlling the threshold voltage (Vth) by adjusting the thickness of the active layer (tactive) rather than by conventional chemical doping in indium-gallium-zinc oxide (IGZO) transistors with an inverted staggered structure. The value of Vth of the IGZO transistor was linearly modulated from −15.3±1.6to−0.1±0.21V by reducing tactive without any significant change in the field-effect mobility (μFE), subthreshold gate swing, or Ion∕off ratio. The free electron density extracted from the relationship between tactive and Vth was 1.9×1017cm−3, which was consistent with the value of 1.5×1017cm−3 obtained from the C-V measurement for the 30-nm-thick IGZO films. The slight increase in the μFE with increasing tactive, which was in contradiction with the behavior of the corresponding amorphous Si transistor, was explained by the anomalous behavior of the source/drain contact resistance.

Modulating indium gallium zinc oxide transistor characteristics with discrete redox states of molecules embedded in the gate dielectric

A hybrid inorganic-organic device has been fabricated by incorporating redox active molecules in indium gallium zinc oxide thin film transistors. These devices show a clear modulation of source-drain current characteristics, which is associated with the quantized energy states of the redox active molecules. The molecules show discreet redox peaks in the current characteristics of transistors and a true-molecular-based charge transport has been demonstrated in a completely solid state device.

Origin of Subthreshold Swing Improvement in Amorphous Indium Gallium Zinc Oxide Transistors

The effect of the channel deposition pressure on the device performance of amorphous indium-gallium-zinc oxide (a-IGZO) transistors was investigated in detail. The performance of the fabricated transistors improved monotonously with decreasing chamber pressure: at a pressure of 1 mTorr, the field-effect mobility (μ FE ) and subthreshold gate swing (S) of the a-IGZO thin-film transistors were dramatically improved to 21.8 cm 2 /Vs and 0.17 V/decade, respectively, compared to those (11.4 cm 2 /Vs and 0.87 V/decade) of the reference transistors prepared at 5 mTorr. This enhancement in the subthreshold characteristics was attributed to the reduction of the bulk defects of the a-IGZO channel, which might result from the greater densification of the a-IGZO films at the lower deposition pressure.