Incremental Analog-to-digital Converter Research Articles

A Two-Phase Multi-Bit Incremental ADC With Variable Loop Order

This brief presents a two-phase multi-bit incremental analog-to-digital converter (IADC) with variable loop order. In the 1st phase, the loop filter works as a 1st-order topology. In the 2nd phase, the loop reconfigures to a 3rd-order structure, aiming to get the signal-to-quantization-noise ratio (SQNR) boosted quickly within a few clock cycles. Such a two-phase scheme with variable loop-order combines the features of the KT/C noise suppression and high effectiveness of data weighting averaging (DWA) presented by the 1st-order IADC and fast accumulation obtained from the high-order mode. Thereby, with little additional circuitry effort, the proposed IADC improves DWA effectiveness while mitigating the thermal noise penalty when compared with a pure high-order IADC. The proposed architecture is analytically analyzed and exemplarily simulated. Moreover, a design guideline is provided to optimize the allocation of the clock cycles of two phases, thus balancing various significant parameters. Based on the guideline, a circuit-level simulation of an exemplary 1st-to-3rd order IADC was carried out in a 65-nm CMOS process to confirm the results.

A Metal-Via Resistance Based Physically Unclonable Function With Backend Incremental ADC

This paper presents a novel physically unclonable function (PUF) for security authentication. Instead of using the variation of transistors or PDK provided passive components as entropy source, the parasitic resistance created between metal and via layers is used as the static entropy source. A symmetric bridge configuration consisted with the parasitic resistance creates the necessary voltage difference for comparison. An accurate backend incremental analog-to-digital converter (IADC) is implemented to convert the voltage difference into a digitized value. The operation of the IADC allows to achieve a good native instability. Two different types of layout structures are implemented to create the necessary parasitic resistance and compared. Fabricated in a 65nm process, the prototype PUF achieves a native instability and bit error rate of less than 1.45% and 0.12% with 5000 repeated evaluations. The proposed design shows 0.58%/0.1V and 0.53%/10°C bit error across the voltage and temperature range of 0.9 to 1.4V and 0°C to 85°C, respectively without any stabilization techniques. The distance ratio between intra-die and inter-die Hamming Distance is above $305\times $ .

Power Bound Analysis of a Two-Step MASH Incremental ADC Based on Noise-Shaping SAR ADCs

Power consumption is an important limitation in designing analog-to-digital converters (ADCs) used in low-power sensing applications. This paper estimates analytically the power bound of a two-step multi-stage noise-shaping successive-approximation-register incremental ADC (two-step MASH NS-SAR IADC) proposed in our previous work. Our model considers the impacts of thermal noise, mismatch, and CMOS process (minimum feature size in CMOS technologies) on the power bounds of the proposed IADC. The analytic results show that thermal noise and CMOS process requirements determine the power consumption lower bounds in high and low resolutions, respectively. A comparison with the most competitive single-loop delta-sigma (ΔΣ) IADC shows a 3-dB higher theoretical figure-of-merit (FoM) for our proposed IADC when the resolutions are higher than 12-bit. Our proposed systematic analysis can be used to estimate the power bounds of amplifier-based NS-SAR ADCs used in either ΔΣ or incremental mode with multi-stage and multi-step topologies designed in various CMOS technologies. The reported analytic results are confirmed by experimental results of previously reported implementations.

Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs

High precision data acquisition requires very-high-resolution Analog-to-digital converters (ADC) for kHz speed or to keep a relatively high resolution for wider bandwidth (BW) around the MHz range. Although widely used, noise-shaping (NS) in ADCs offers a high-resolution characteristic, but obtaining good power efficiency and compact die area is still challenging. Recent literature showed promising progress by utilizing hybrid Discrete-Time (DT) NS-ADCs with measured silicon results. This paper focuses its analysis and discussion on two important trending classes: hybrid Incremental ADCs (I-ADC) and hybrid Time-interleaved (TI) NS-ADCs. Furthermore, this paper presents a review and addresses the benefits of those hybrid architectures.

Incremental Delta-Sigma ADCs: A Tutorial Review

In many sensor applications, a high-resolution analog-to-digital converter (ADC) is a key block. The use of an incremental delta-sigma ADC (IADC) is often well suited for such applications. While the energy-efficiency of IADCs has improved by several orders of magnitude over the past decade, the implementation of high performance IADCs, especially in battery-powered systems, is still challenging. This paper presents a tutorial review on energy-efficient IADCs and addresses the progress in this area. This paper describes the fundamentals of IADCs and energy-efficient hybrid IADC architectures. Various design techniques for improving the energy-efficiency of the IADCs are described. This paper is intended to serve as a starting point for the development of a new energy-efficient IADC.

A 5.2-Mpixel 88.4-dB DR 12-in CMOS X-Ray Detector With 16-bit Column-Parallel Continuous-Time Incremental ΔΣ ADCs

This article presents a 5.2-Mpixel, 12-in wafer-scale CMOS X-ray detector that consists of lithographically stitched 169 sub-chips. The detector employs a 3T pixel with a voltage-controlled storage capacitor to achieve both a low dark random noise (RN) and a large well capacity, and the pixel outputs are read out by column-parallel continuous-time (CT) incremental delta-sigma (ΔΣ) analog-to-digital converters (ADCs). The use of a CT incremental ΔΣ ADC enables high resolution and low energy consumption while securing uniformity and robustness over the 12-in wafer. This work is fabricated in a 1P4M 65-nm CMOS technology. The 16-bit ADC implemented within a 45-μm pitch achieves a differential nonlinearity (DNL) of +0.79/-0.65 LSB, an integral nonlinearity (INL) of +6.85/-6.15 LSB, and a peak signal-to-noise ratio (SNR) of 88.5 dB with a conversion time of 12.6 μs. This detector achieves a CFPN of 181 μV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> , a dark RN of 267 μV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> , and a DR of 88.4 dB while consuming 3.9 W at 30 frames/s. Compared with the state of the arts, this work achieves 3× larger spatial resolution, 1.8× higher pixel rate, 1.9× higher energy-efficiency, and 17 dB higher DR, simultaneously.

A triple-channel incremental zoom-ADC for 3-DoF MEMS digital gyroscopes

This paper presents a multiplexed analog-to-digital converter (ADC) consisting mainly of high-precision sampling holders (S/H) and an incremental zoom ADC. Flip-around design is employed in S/H modules for power economy and noise suppression. Based on efficient coordination between S/H and multiplexers, synchronous sampling is available in the whole triple-channel ADC to maintain phase accordance. The core converter employed a hybrid architecture of successive approximation register (SAR) and Sigma-Delta [Formula: see text], which constitutes an energy-efficient zoom ADC. Final conversion result is a combination of the two steps. Both the SAR and [Formula: see text] modulation share a third-order loop filter to compromise between systematic stability and input range. On-chip digital logic include capacitor array controlling and dynamic-element-matching (DEM) technique. Manufactured in a standard [Formula: see text]m CMOS technology, the whole chip occupies an area of 2.7 mm2. Experimental results show a maximum signal-to-noise ratio (SNR) of 100.2 dB, with a power consumption of 2.1 mW from a 5 V supply.

A 102.2-dB, 181.1-dB FoM Extended Counting Analog-to-Digital Converter With Capacitor Scaling

Sensor interfaces demand ever-increasing energy efficiency from analog-to-digital converters (ADCs). For sensors requiring a wide dynamic range (DR) (>12 bit), the incremental ADC (IADC) is becoming a popular choice. In this article, the design of an energy-efficient IADC with a 16-bit signal-to-noise and distortion ratio (SNDR) and 17-bit DR is described. The IADC implements a novel capacitor scaling technique, which reduces power consumption in the critical first operational transconductance amplifier (OTA) by up to 37%. The new technique can be combined with the extended counting (EC) scheme utilizing an in-loop 4-bit asynchronous successive approximation register (SAR) (ASAR) ADC. Using a three-phase operation, this IADC architecture further reduces the power while enabling wider signal bandwidth with a much lower oversampling ratio (OSR). Silicon measurements in a 0.18- $\mu $ m CMOS process show the IADC achieved a DR of 102.2 dB, within a bandwidth of 2.04 kHz, with power consumption of about $25~\mu $ W, leading to a state-of-the-art Schreier figure-of-merit (FoM) of 181.1 dB.

A 550-$\mu$ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental $\Sigma\Delta$ ADC With 256 Clock Cycles in 65-nm CMOS

This paper presents an incremental analog-todigital converter (IADC) with a two-phase linear-exponential accumulation loop. In the linear phase, the loop works as a first-order structure. The noise-coupling (NC) path is then enabled in the exponential phase thus boosting the signalto-quantization-noise ratio (SQNR) exponentially with a few number of clock cycles. The two-phase scheme combines the advantages of the thermal noise suppression in the first-order IADC and SQNR boosting in the exponential mode. The uniformexponential weight function allows the data weighted averaging (DWA) technique to work well, leading to the rotation of the multi-bit DAC mismatch error. Meanwhile, this scheme does not destroy the notches, which can be utilized to suppress the line noise. Implemented in 65-nm CMOS under 1.2V supply, the analog-to-digital converter (ADC) achieves an signal-to-noise + distortion ratio (SNDR)/dynamic range (DR) of 100.8 dB/101.8 dB with 20-kHz bandwidth (BW), 550 μW, and 0.134 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , resulting in Walden/Schreier FoMW/FoMS of 153 fJ/176.4 dB, respectively. The differential and integral nonlinearities are +0.27 LSB/-0.27 LSB and +0.84 LSB/-0.81 LSB, respectively.

A Triple-Mode Performance-Optimized Reconfigurable Incremental ADC for Smart Sensor Applications

This paper proposes a triple-mode discrete-time incremental analog-to-digital converter (IADC) employing successive approximation register (SAR)-based zooming and extended counting (EC) schemes to achieve programmable trade-off capability of resolution and power consumption in various smart sensor applications. It mainly consists of an incremental delta–sigma modulator and the proposed SAR-EC sub-ADC for alternate operation of the coarse SAR conversion and EC. They can be reconfigured to operate separately depending on the application requirements. The SAR-based zooming structure allows the IADC to have better linearity and resolution, and additional activation of the EC function gives the further resolution. During this reconfigurable conversion process, pipelined reusing operation of sub-blocks reduces the silicon area and the number of cycles for target resolutions. A prototype ADC is fabricated in a 180-nm CMOS process, and its triple-mode operation of high-resolution, medium-resolution, and low-power is experimentally verified to achieve 116.1-, 109.4-, and 73.3-dB dynamic ranges, consuming 1.60, 1.26, and 0.39 mW, respectively.

Power Bounds and Energy Efficiency in Incremental &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\Delta\Sigma$ &lt;/tex-math&gt; &lt;/inline-formula&gt; Analog-to-Digital Converters

Incremental analog-to-digital-converters (IADCs) are variants of $\triangle \Sigma $ ADCs, which have been increasingly used for low-power sensory applications in recent years. Most IADC applications require high resolution and high energy efficiency. In this paper, we present a systematic analysis of IADCs. We derive analytical design equations for practical IADC designs. Process limitations are included in the model as well. The equations are verified with a 14-bit second-order IADC design in a 0.18- $\mu \text{m}$ process. With the design equations, the theoretical energy efficiency bound is derived for IADCs. The efficiency bound is compared with previously reported IADC designs. It is found that the derived bound matches existing designs well.

A 1.25 MS/s Two-Step Incremental ADC With 100-dB DR and 110-dB SFDR

This letter presents a two-step incremental analog-to-digital converter (IADC) with extended counting. The proposed IADC has only one active integrator in the two-step conversion cycle. To achieve high accuracy without trimming or calibration, a cyclic analog-to-digital converter (ADC) with a 31-level quantizer is used in the second step. The ratio of the amplification in the second step is 2.25 (> 2), which leads to exponential resolution improvement by 2.25 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> in 8 cycles. Fabricated in 0.18-μm CMOS process, the prototype ADC occupies 0.72 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . With a 55-MHz clock, the measured dynamic range and the SFDR are 100 dB and 110 dB, respectively, at a conversion rate of 1.25 MS/s. The power consumption is 27.7 mW from a 3-V power supply. This gives a Schreier FoM of 173.6 dB.

A 16 b Multi-Step Incremental Analog-to-Digital Converter With Single-Opamp Multi-Slope Extended Counting

This paper presents a multi-step incremental analog-to-digital converter (IADC) using multi-slope extended counting. Only one active integrator is used in the three-step conversion cycle. The accuracy of the IADC is extended by having it configured asmulti-slope ADCs in two additional steps. The proposed IADC uses the same circuitry as a first-order IADC (IADC1), but it exhibits better performance than a second-order IADC. For the same accuracy, the conversion cycle is shortened by a large factor (by more than 29 for the implemented device) compared with that of a conventional single-step IADC1. Fabricated in 0.18 $\mu \text{m}$ CMOS process, the prototype ADC occupies 0.5 mm2. With a 642 kHz clock, it achieves an SNDR of 52.2 dB in the first step. The SNDR is boosted to 79.8 dB in the second step and to 96.8 dB in the third step, over a 1 kHz signal band. The power consumption is 35 $\mu \text{W}$ from a 1.5 V power supply. This gives an excellent Schreier figure of merit of 174.6 dB.

A 95-dB DR second order incremental ΣΔ ADC for multi-channel healthcare application

To meet the requirement of multi-channel healthcare applications, a second order incremental ΣΔ analog-to-digital converter (ADC) in 0.35 μm CMOS technology is proposed for minimizing power consump...

A Power-Efficient Continuous-Time Incremental Sigma-Delta ADC for Neural Recording Systems

This paper presents an analog-to-digital converter (ADC) dedicated to neural recording systems. By using two continuous-time incremental sigma-delta ADCs in a pipeline configuration, the proposed ADC can achieve high-resolution without sacrificing the conversion rate. This two-step architecture is also power-efficient, as the resolution requirement for the incremental sigma-delta ADC in each step is significantly relaxed. To further enhance the power efficiency, a class-AB output stage and a dynamic summing comparator are used to implement the sigma-delta modulators. A prototype chip, designed and fabricated in a standard 0.18 μm CMOS process, validates the proposed ADC architecture. Measurement results show that the ADC achieves a peak signal-to-noise-plus-distortion ratio of 75.9 dB over a 4 kHz bandwidth; the power consumption is 34.8 μW, which corresponds to a figure-of-merit of 0.85 pJ/conv.

Current Input Extended Counting ADC With Wide Dynamic Range for LWIR FPAs

A readout circuit incorporating a pixel level analog-to-digital converter (ADC) is studied for 2-D long wavelength infrared focal plane arrays (LWIR FPAs). The charge handling capacity of the unit cell circuit is improved by using the current input incremental ADC. The proposed pixel level ADC is based on an extended counting ADC but is composed of two oversampling conversions. The readout circuit has been fabricated using a 0.35 mum 2-poly 4-metal CMOS process for a 128 times 128 LWIR HgCdTe array with a pixel size of 50 mum times 50 mum. The peak signal-to-noise ratio (S/N) and dynamic range (DR) were measured to be 85.8 dB and 99.9 dB, respectively, with a total power consumption of 50 mW.