Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs

Dongyang Jiang,Liang Qi,Rui P. Martins,Sai-Weng Sin,Guoxing Wang

doi:10.1109/ojsscs.2021.3118668

Abstract

High precision data acquisition requires very-high-resolution Analog-to-digital converters (ADC) for kHz speed or to keep a relatively high resolution for wider bandwidth (BW) around the MHz range. Although widely used, noise-shaping (NS) in ADCs offers a high-resolution characteristic, but obtaining good power efficiency and compact die area is still challenging. Recent literature showed promising progress by utilizing hybrid Discrete-Time (DT) NS-ADCs with measured silicon results. This paper focuses its analysis and discussion on two important trending classes: hybrid Incremental ADCs (I-ADC) and hybrid Time-interleaved (TI) NS-ADCs. Furthermore, this paper presents a review and addresses the benefits of those hybrid architectures.

Highlights

H IGH resolution Analog-to-digital converters (ADC) are crucial building blocks in consumer electronics, especially for high precision sensors in the Internet of everything (IoE), audio codecs, and wearable healthcare applications
We review two classes of hybrid high-resolution NS-ADC architectures: 1) for subMHz frequency, incremental ADC (I-ADC) has been widely used for ultra-high-resolution designs [8]–[16]
High-resolution ADCs have primarily been achieved by Noise-shaping techniques

Summary

INTRODUCTION

H IGH resolution ADCs are crucial building blocks in consumer electronics, especially for high precision sensors in the Internet of everything (IoE), audio codecs, and wearable healthcare applications. With the first OTA’s input/output nodes still connected, such hybrid architecture leads to the proposed sliced I-ADC in [15], dynamically reconfiguring the input loop filter stage with a slight signal power weakening. With the optimized clock cycle parameters (k0,1,2,3 = 40, 30, 10, 70), this prototype consumes 1.65-mW/1.098-mW without/with the slicing technique from a 3V supply, which results in only 0.7dB/0.8dB loss in SNR/SNDR, respectively This ADC, fabricated in 180nm CMOS, has a peak SNDR of 86.6dB in a 100kHz BW, achieving a FoMs of 171.1 dB. The application of such techniques are in CT, they are applicable in the DT counterpart, with the benefits of reducing the high-frequency quantization noise in the integrators, relax the opamp’s slew rate requirement, and the distribution of the FIR filter tap coefficients along different interleaving paths

TI NS-ADC BASED ON AN N-PATH FILTER

Findings

CONCLUSION