A sinusoidal reference signal based high accuracy timing skew mismatch estimation scheme for time interleaved ADC

Abstract

This paper proposed a reference signal based timing skew estimation scheme for time interleaved (TI) analog to digital convertor (ADC). A sinusoidal reference signal is employed to estimate the timing skew mismatch between the sub-channel ADCs. The reference signal is a filtered sinusoidal signal, thus it takes only a very small bandwidth to achieve better anti-interference capability. Generated by the same clock management unit which generates the sampling clock of the sub-ADCs, the reference signal does not require additional circuits, and provides the system with real-time tracking capability against environmental changes. And there is no frequency error/jitter between the digital domain clock and the reference signal, thereby reducing the consumption of computational resources for signal frequency synchronization. Simulation results shows that the estimation error is only 5.8 fs when the timing skew is 100 fs, which is comparable as the jitter performance of the TI ADC's typical sampling clock.