A Two-Phase Multi-Bit Incremental ADC With Variable Loop Order

Abstract

This brief presents a two-phase multi-bit incremental analog-to-digital converter (IADC) with variable loop order. In the 1st phase, the loop filter works as a 1st-order topology. In the 2nd phase, the loop reconfigures to a 3rd-order structure, aiming to get the signal-to-quantization-noise ratio (SQNR) boosted quickly within a few clock cycles. Such a two-phase scheme with variable loop-order combines the features of the KT/C noise suppression and high effectiveness of data weighting averaging (DWA) presented by the 1st-order IADC and fast accumulation obtained from the high-order mode. Thereby, with little additional circuitry effort, the proposed IADC improves DWA effectiveness while mitigating the thermal noise penalty when compared with a pure high-order IADC. The proposed architecture is analytically analyzed and exemplarily simulated. Moreover, a design guideline is provided to optimize the allocation of the clock cycles of two phases, thus balancing various significant parameters. Based on the guideline, a circuit-level simulation of an exemplary 1st-to-3rd order IADC was carried out in a 65-nm CMOS process to confirm the results.