In-plane Gate Transistors Research Articles

In-plane gate graphene transistor with epitaxially grown molybdenum disulfide passivation layers

We demonstrate in-plane gate transistors based on the molybdenum disulfide (MoS2)/graphene hetero-structure. The graphene works as channels while MoS2 functions as passivation layers. The weak hysteresis of the device suggests that the MoS2 layer can effectively passivate the graphene channel. The characteristics of devices with and without removal of MoS2 between electrodes and graphene are also compared. The device with direct electrode/graphene contact shows a reduced contact resistance, increased drain current, and enhanced field-effect mobility. The higher field-effect mobility than that obtained through Hall measurement indicates that more carriers are present in the channel, rendering it more conductive.

Printed in-plane electrolyte-gated transistor based on zinc oxide

Printed electronics is a reputable research area that aims at simple alternatives of manufacturing low-cost, eco-friendly, and biodegradable electronic devices. Among these devices, electrolyte-gated transistors (EGTs) stand out due to their simple manufacturing process and architecture. Here we report the study of printed EGTs with in-plane gate transistor (IPGT) architecture based on zinc oxide nanoparticles. The drain, source, and gate electrodes with two different W/L channel ratios were fabricated using a screen-printed carbon-based ink. We also produced a conventional top-gate transistor as a standard device, using the same structure of the IPGT described above with the addition of an indium tin oxide strip positioned over the electrolyte as the top-gate electrode. The IPGT with W/L = 5 presented a high mobility of 7.95 ± 0.55 cm2 V−1 s−1, while the W/L = 2.5 device exhibited a mobility of 3.03 ± 0.52 cm2 V−1 s−1. We found that the measured field-effect mobility of the device can be affected by the high contact resistance from the carbon electrodes. This effect could be observed when the device’s geometric parameters were changed. Furthermore, we also found that the IPGT with W/L = 5 exhibited higher values for mobility and transconductance than the top-gate transistor, showing that the IPGTs architecture is a good approach for cheap and printed transistors with performance comparable to standard top-gate EGTs.

Long-Wavelength In-Plane Gate InAs Quantum-Dot Phototransistors

In-plane gate transistors with and without an InAs quantum-dot (QD) absorption layer are investigated. The n-GaAs channel acts as both an absorption layer for incident light with energy higher than the GaAs bandgap and the transport path for the photocurrents. The insertion of InAs QD layer not only extends the absorption wavelength to $1.26~\mu $ m, but also enhances the optical response from GaAs.

Memory device application of wide-channel in-plane gate transistors with type-II GaAsSb-capped InAs quantum dots

We demonstrate room-temperature electron charging/discharging phenomena of InAs quantum dots using wide-channel in-plane gate transistors. The device based on type-II GaAsSb-capped InAs quantum dots exhibits both the longer charging and discharging times than those of the type-I counterpart with GaAs capping layers. The slow charge relaxation of GaAsSb-capped InAs quantum dots and simple architecture of in-plane gate transistors reveal the potential of this device architecture for practical memory applications.

In-Plane Gate Transistors for Photodetector Applications

In-plane gate transistors (IPGTs) with 20-μm channel widths are fabricated on samples with <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> -(InGa)As sheet resistance embedded in undoped GaAs matrix. A trade-off between effective current modulation and high saturation drain current is obtained by optimizing the doping density of the sheet resistance. The mechanism responsible for the transistor behaviors of the devices is due to the channel electron depletion related to the population of mobile surface electrons under different gate biases. The photocurrent measurements demonstrate that the IPGT architecture is a feasible approach for the applications of photodetectors.

In-Plane Gate Transistors With a 40-$\mu\hbox{m}$-Wide Channel Width

An in-plane gate transistor with a GaAs/AlGaAs 2-D electron-gas channel about 40 μm in width is investigated. The saturation region and the drain current modulation at different gate bias voltages are observed despite the wide channel. The surface-induced channel depletion is suggested as the main mechanism for the turn-off of the drain current at - 10 V gate bias.

Operating principle and integration of in-plane gate logic devices

Logic devices based on in-plane gate (IPG) transistors are realized and their electrical characteristics and integration are investigated. We present logic devices based on lateral gate structures using an additional IPG transistor as a load resistance. These logic devices show clear input-output characteristics and voltage transfer curves as a logic device and the Hi/Low ratio is high enough for reliable logic operations. Furthermore, the IPG logic devices operate at low current levels. Monolithic NOT-gate is demonstrated and the number of terminals and wiring are considerably reduced by using our IPG logic devices compared to logic devices based on CMOS transistors.

Electrical characteristics of in‐plane gate logic devices

AbstractLogic devices based on in‐plane gate (IPG) transistors are realized and their electrical characteristics are investigated. An IPG transistor connected in series with a resistance functions as a logic device. In this work, we present logic devices based on lateral gate structures using an additional IPG transistor as a variable resistance. The logic device is formed by an in‐plane double gate transistor connected in series with a self‐gating transistor as a variable resistance. It shows clear input‐output characteristics as a logic device. Either NAND or NOR operation can be achieved by changing the width of the self‐gating transistor. The operation of IPG logic devices depends on the resistance ratio of the two transistors. By using IPG transistors as variable resistances, the Hi/Low ratio is high enough for reliable logic operations. Furthermore, it is shown that the number of terminals and wiring are considerably reduced by using our IPG logic devices compared to logic devices based on CMOS transistors. (© 2012 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

In-Plane Gate Transistors Fabricated by Using Atomic Force Microscopy Anode Oxidation

An in-plane gate transistor fabricated by using the atomic force microscopy (AFM) lithography is investigated in this letter. By performing repeated oxidation and deoxidation procedures by using the AFM for four times, two V-shaped trenches are fabricated on the prepatterned mesas to isolate the electrical terminals of the device. Without exposing the channel region to the atmosphere, the device has exhibited standard transistor current-voltage characteristics in the 0-5 V range at room temperature, which may be advantageous for the future high-speed application of the device.

Negative Differential Resistance in InGaAs/InAlAs Nanoscale In-Plane Structures

Nanoscale in-plane structure devices are fabricated by electron beam lithography followed by electron cyclotron resonance reactive ion etching. We investigate the negative differential resistance (NDR) of InGaAs/InAlAs in-plane structure devices. The NDR appears in the current–voltage (I–V) characteristics of simple two-terminal in-plane short-channel devices. NDR characteristics depend on the effective channel width of in-plane gate transistors and become more pronounced when the channel conductance is increased by applying gate voltages. In a short-channel in-plane gate transistor, a more prominent NDR is observed and the NDR appears even at room temperature. In addition, the NDR onset voltage shifts to lower voltages when the channel length decreases. The NDR phenomenon is most likely caused by the real-space transfer of electrons from a high mobility channel to a low mobility layer.

In-plane gate transistors implanted with different channel geometries by focussed ion beam in positive mode pattern definition technique

In-plane gate (IPG) transistors with various channel geometries have been fabricated by focus ion beam implantation technique in positive pattern definition mode on GaAs/AlxGa1−xAs heterostructures. Both n- and p-type channel transistors were obtained for either n- or p-doped heterostructures, by implantation of the channel or the gate regions with the complementary dopant type to compensate the initial doping. The current–voltage characteristics showed that the channel can be fully controlled by a gate bias, i.e., it can be completely depleted or enhanced, but two gates are needed to control the channel. Different channel geometries were studied, the most efficient being the “Z-shaped” one. The n-type channel IPG transistors present source–drain currents of few hundreds of microamperes, which is two to three orders of magnitudes higher than that for the p-type channel ones.

A sequential logic device realized by integration of in-plane gate transistors in InGaAs∕InP

An integrated nanoelectronic circuit is fabricated from a high-mobility In0.75Ga0.25As∕InP heterostructure. The manufactured device comprises two double in-plane gate transistors with a current channel of 1.1μm in length and 100nm in width. The two transistors are coupled to each other in a configuration that the source of one transistor is directly connected with one in-plane gate of the other transistor. Electrical measurements reveal that this device functions as an SR (set-reset) latch (a sequential logic device) with a gain of ∼4 in the logic swing at room temperature. The demonstrated device provides a simple circuit design for SR latches.

Electrostatic electron piston pump with in‐plane gate transistors

AbstractWe have demonstrated an electron pump with in‐plane gate (IPG) transistors fabricated by focused ion beam (FIB) implantation on GaAs–Alx Ga1–x As modulation‐doped heterostructure with a two‐dimensional electron gas (2DEG). The maskless fabrication process does not require any alignment between the circuit elements including the sources, the drains and the gates of the IPG transistors. Although, the device is operating at low frequencies (tens of kHz), it is capable to produce a current more than one order of magnitude higher than other electron pumps based on Coulomb blockade and single electron tunneling effects. (© 2007 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Kelvin force microscopy on diamond surfaces and devices

The results, resolution and accuracy of Kelvin force microscopy (KFM) on highly conductive (hydrogenated) and highly resistive (oxidized) diamond surfaces are discussed in detail. Electronic properties of the interface between hydrogen and oxygen terminated surface regions are investigated using KFM profiles across in-plane gate transistor structures. Measurements under sub-band gap illumination are interpreted in terms of a surface photovoltage effect and are used to deduce information about surface and interface states.

Fabrication of two-dimensional n- and p-type in-plane gate transistors from the same p-doped GaAs/In 0.1Ga 0.9As/Al 0.33Ga 0.67As heterostructure

We have fabricated n- as well as p-channel in-plane gate transistors by focused compensation doping of a p-doped pseudomorphic GaAs/In 0.08Ga 0.92As/Al 0.33Ga 0.67As heterostructure. Both types show transistor operation with higher drain currents for the n-channel version. Both types could be completely depleted. Only the n-channel transistors show drain current saturation with the increasing drain–source voltage.

In-plane gate transistors in Al xGa 1− xN/GaN heterostructures written by focused ion beams

Focused ion beam implantation of gallium and dysprosium was used to locally insulate the near-surface two-dimensional electron gas of Al x Ga 1− x N/GaN heterostructures. The threshold dose for insulation was determined to be 2×10 10 cm −1 for 90 keV Ga + and 1×10 9 cm −1 for 200 keV Dy 2+ at 4.2 K. This offers a tool not only for inter-device insulation but also for direct device fabrication. Making use of “open-T” like insulating line patterns, in-plane gate transistors have been fabricated by focused ion beam implantation. An exemplar with a geometrical channel width of 1.5 μm shows a conductance of 32 μS at 0 V gate voltage and a transconductance of around 4 μS, which is only slightly dependent on the gate voltage.

Fabrication of in-plane gate transistors on hydrogenated diamond surfaces

The highly conductive surface layer induced in diamond by hydrogen termination has been used to fabricate in-plane gate transistors. The conductive channel has been separated from the Ohmic gate contacts by insulating thin lines, obtained by using a combination of electron-beam lithography with surface oxidation. Oxidized lines of about 100 nm show excellent blocking properties, with leakage current of 0.3 pA/μm at 100 V and room temperature. In-plane transistor properties are reported for operation at 77 K and room temperature with good saturation characteristic and complete pinch-off.

Diamond cantilever with integrated tip for nanomachining

Atomic force microscopy was successfully applied for the reproducible nanomachining of in-plane gate transistors made from GaAs/AlGaAs heterostructures. Electronic devices with structures of less than 50 nm dimensions were realized by scribing with a pointed cantilever probe. This process demands tips made of an extreme hard material with sufficiently low abrasion. For this purpose all-diamond cantilever probes made of polycrystalline diamond films were proven to be ideally suited. The separate definition of the lateral and vertical probe geometry during diamond cantilever fabrication offers important advantages in comparison to conventionally moulded probes that will be discussed in some detail.

Fabrication of two-dimensional in-plane gate transistors by focused ion beam doping

In-plane-gate (IPG) transistors have been fabricated using focused ion beam implantation doping of GaAs/In 0.1Ga 0.9As/Al 0.35Ga 0.65As heterostructures. At room temperature in the dark, the devices show good transistor characteristics and—in contrast to IPG transistors defined by insulation writing using ion implantation—the observed enhancement behavior is very good. For typical devices the source–drain current in the saturation region of 1.6 μA at zero gate voltage could be increased by one order of magnitude to 16 μA by a positive gate voltage of 8 V . This improvement in the enhancement behavior with respect to IPG transistors defined by insulation writing is attributed to the higher electronic transport quality in the edge regions of the channel. The gate leakage current for typical operation parameters is below 350 nA and at a gate voltage of −1 V the channel is completely pinched off.

Study of the hot spot of an in-plane gate transistor by scanning Joule expansion microscopy

The local heat dissipation of an in-plane gate (IPG) transistor was investigated by means of a thermally modulated scanning Joule expansion microscope. The nanostructured sample was prepared by focused ion beam techniques. The temperature induced thermal expansion and the topographic information are measured simultaneously. The spatial resolution of the constructed microscope is below 50 nm. Heat spots of the semiconducting devices are visualized by heating them with modulated drain voltage. The heat spot position and the temperature amplitude of the heat spot on the IPG transistor depend on the gate voltage VG. With an increasing negative magnitude of VG the heat spot displaces in the direction from drain towards source. Simultaneously the temperature amplitude of the maximum of the heat spot and the thermal expansion integrated over the heated area decrease linearly.