Improvement In Subthreshold Swing Research Articles

Stability and gap states of amorphous In-Ga-Zn-Ox thin film transistors: Impact of sputtering configuration and post-annealing on device performance

Stability of amorphous In-Ga-Zn-Ox (a-IGZO) thin-film-transistors (TFTs) is studied from a viewpoint of gap states, associated with oxygen-related defects and structural disordering. The a-IGZO gap states are controlled through the film preparation by magnetron sputtering under two different configurations and post-annealing in oxygen atmosphere. The distribution of gap states is then evaluated from the subgap absorption spectrum, which is measured by a constant photocurrent measurement technique. With this known distribution, a-IGZO TFTs are fabricated, and the stability of the TFT performances is examined through the negative bias induced stability (NBIS) experiments. The results suggest that a negative threshold voltage shift, induced by NBIS, is improved by reducing the density of gap states, i.e., narrowing the gap state distribution. The reduction of gap states also contributes to the improvement of subthreshold swing.

A new line tunneling SiGe/Si iTFET with control gate for leakage suppression and subthreshold swing improvement

This article presents a new line tunneling dominating metal–semiconductor contact-induced SiGe–Si tunnel field-effect transistor with control gate (CG-Line SiGe/Si iTFET). With a structure where two symmetrical control gates at the drain region are given a sufficient negative bias, the overlap of the energy bands at the drain in the OFF-state is effectively suppressed, thus reducing the tunneling probability and significantly decreasing leakage current. Additionally, the large overlap area between the source and gate improves the gate’s ability to control the tunneling interface effectively, improving the ON-state current and subthreshold swing characteristics. By using the Schottky contact characteristics of a metal–semiconductor contact with different work functions to form a PN junction, the need to control doping profiles or random doping fluctuations is avoided. Furthermore, as ion implantation is not required, issues related to subsequent annealing are also eliminated, greatly reducing thermal budget. Due to the different material bandgap characteristics selected for the source and drain regions, the probability of overlap of the energy bands in the source region in the ON-state is increased and that in the drain region in the OFF-state is reduced. Based on the feasibility of the actual fabrication process and through rigorous 2D simulation studies, improvements in subthreshold swing and high on/off current ratio can be achieved simultaneously based on the proposed device structure. Additionally, the presence of the control gate structure effectively suppresses leakage current, further enhancing its potential for low-power-consumption applications.

Characterization and compact modeling of short channel MOSFETs at cryogenic temperatures

This paper presents an overall characterization, physics-based device analysis, and compact modeling of a commercial 110nm bulk CMOS technology. I−V measurements and DC parameters extraction are performed on low threshold voltage (low VTH, LVT) and regular VTH (RVT) devices with various geometry dimensions from 300 K to 6 K. Different levels of improvement of subthreshold swing (SS), OFF-state current (IOFF), and mobility indicates the potential to optimize the performance of circuits at cryogenic temperatures. However, the temperature characteristics of the mobility and series resistance show a great dependence on the channel length of the devices, which complicates the calculation of the ON-state current at cryogenic temperatures. Moreover, VTH roll-off caused by short channel effect (SCE) get worse, which can be attributed to the increased bulk Fermi potential (ϕf). These channel-length-related effects add extra challenges to the design of cryogenic circuits. An optimized compact model based on BSIM4 is proposed to capture the device characteristics at 6 K, which can produce accurate simulation results only through parameter configuration rather than model equation modification and has been applied to the design of cryogenic CMOS circuits.

Improved Subthreshold Swing of MoS₂ Negative-Capacitance Transistor by Using HfZrAlO as Ferroelectric Layer of Gate-Stack

In this work, a hafnium–zirconium–aluminum–oxide (HZAO) is proposed and atomic layer deposition (ALD), and its ferroelectricity is shown to be stronger than hafnium–zirconium–oxide (HZO) by measuring polarization versus electric field ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P} - {E}$ </tex-math></inline-formula> ) loop. Also, a large sharp peak of capacitance–voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C} - {V}$ </tex-math></inline-formula> ) curve is observed in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C} - {V}$ </tex-math></inline-formula> measurement to confirm the strong negative-capacitance (NC) effect. The fabricated MoS2 NCFET using HZAO as a ferroelectric layer of gate-stack exhibits a significantly reduced subthreshold swing (SS) (17 mV/dec almost over four orders of drain current magnitude, with a minimal SS of 12.8 mV/dec) as compared to its counterpart with the HZO ferroelectric layer (a minimal SS of 38.5 mV/dec). The involved mechanisms lie in that incorporation of Al atoms into the HZO film can form the additional hafnium–aluminum–oxide (HAO) and zirconium–aluminum–oxide with ferroelectricity, and as a result, the formed composite HZAO film can convert more monoclinic phases to orthorhombic phase than the HZO film, leading to stronger ferroelectricity for the former than the latter and, thus, smaller SS for its relevant NCFET.

Analysis of total ionizing dose response of optimized fin geometry workfunction modulated SOI-FinFET

The total ionizing dose (TID) response of SOI-FinFET with linear gate workfunction modulation is presented and evaluated. The gate metal workfunction is linearly modulated from source to drain to maintain the electrostatic integrity of the device. At the higher radiation dose (2000 krad), the proposed device has shown reduced Off-current by 2-decade leads to improvement in current switching ratio. Moreover, the proposed device offers 9% and 3% improvement in subthreshold swing before and after the radiation, respectively. During irradiation the trap charges are found in the BOX layer and SiO2/Si interface. These charges contributed towards shifting of threshold voltage (Vth). The linear workfunction modulation shows a 73% more Vth as compared to single workfunction FinFET for radiation of 2000 krad dose. As per simulation results, the proposed device is reliable and capable to sustain in the radiation environment.

Scallop-shaped p-type FinFETs with improved short-channel effects immunity and driving current

In this work, scallop-shaped p-type fin field-effect transistors (S-FinFETs) that outperform control-FinFETs for a given gate length are fabricated based on a conventional high-к metal gate FinFET fabrication flow. Because of the scallop-shaped gate structure and ultra-thin (∼5 nm) S-fin channel, the S-FinFETs demonstrate a 25% improvement in subthreshold swing and a 54% decrease in drain-induced barrier lowering compared with those of the control-FinFETs for a 20 nm physical gate length. Furthermore, a driving current of 200 μA/μm is obtained for S-FinFETs with a source/drain epitaxial substrate and a gate length of 20 nm, matching the performance of control-FinFETs with a source/drain epitaxial substrate. With improved short-channel effect immunity, the proposed S-FinFET provides a promising candidate beyond-FinFET technology.

Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes

In this paper, for the first time, we have investigated the DC, analog/RF, and linearity metrics of asymmetric spacer junctionless (JL) Gate-All-Around (GAA) vertically stacked nanowire field-effect-transistor (FET) for significantly enhanced performance at sub-5 nm nodes. The symmetric and asymmetric spacer lengths are optimized and compared towards the improvement of subthreshold swing (SS) and switching (IONIOFF) behavior with various spacer dielectrics. For optimal values of source (LS) and drain (LD) spacer lengths, the device IONIOFF ratio has an improvement of 22.69% and a reduction in IOFF by 34.13% as compared to other variations. Our study reveals that, in symmetric spacer variations the device exhibits superior performance with LS=LD=1.5×LG. However, compared to symmetric, the asymmetric spacer exhibits higher IONIOFF and lower SS with LS=1.5×LG and LD=2.5×LG. Moreover, LG scaling impact on SS, DIBL, Vth, and ION are reported with various spacers. The optimized asymmetric spacer exhibits excellent DC characteristics with SS of 64 mV/dec and IONIOFF ratio of ∼108 even for 5 nm gate length (LG) ensures fundamental scaling. At LG of 10 nm with asymmetric spacer, a cut-off frequency (fT) = 0.4 THz, gain-bandwidth product (GBW) = 0.08 THz, and intrinsic delay (τ) = 1.3 ps are achieved. Finally, the device exhibits second order harmonic (gm2) = 0.2 mA/V2 and third order harmonic (gm3) = 1.1 mA/V3 at nano-regime. Thus optimally designed JL nanowire FET ensures potential candidate towards low-power, high frequency, and better linearity for future technology nodes.

Hydrophobic Polymer Encapsulation Effects on Subgap Density of States in Multilayered Molybdenum Disulfide Field‐Effect Transistors

Herein, exfoliated, multilayered molybdenum disulfide (MoS2) (m‐MoS2) field‐effect transistors (FETs) are implemented with bilayered SiNx/SiOx gate dielectrics on indium tin oxide (ITO) substrates. For a quantitative understanding on gas adsorption effects on the electrical performance of m‐MoS2 FETs, subgap density of states (DOSs) in m‐MoS2 layers without (or with) hydrophobic polymer encapsulation are extracted using optical charge‐pumping capacitance–voltage spectroscopy. Based on extracted subgap DOSs and their deconvolution with analytical model of acceptor (or donor) like states, all electrical parameters are systematically analyzed. More importantly, two times increase in field‐effect mobility (μFE) is strongly related with decrease in shallow donor states (NSD) from 2 × 1018 to 2 × 1017 eV−1 cm−3. In addition, significant improvement of subthreshold swing (SS), hysteresis gap (VHYS) are attributed to the reduction of tail states (NTA) from 4 × 1019 to 2 × 1019 eV−1 cm−3, along with decrease in midgap states (NMid) from 3 × 1016 to 1.3 × 1016 eV−1 cm−3. For a final validation, technology computer‐aided design (TCAD) simulation with extracted DOS information nicely replicate measured I–V characteristics for m‐MoS2 FETs without (or with) encapsulation, indicating that extracted DOS information is quite accurate, compared with implemented m‐MoS2 FETs.

Abnormal Back Channel Leakage Under Large Drain Voltage in Short Channel Organic Thin-Film Transistors

This study investigates short channel (length $ ) p-type organic thin-film transistor (OTFT) devices which exhibit off-state leakage in their ID–VG characteristics. This phenomenon is attributed to the fact that when a lower positive gate voltage is applied, gate voltage cannot control the back channel, causing back channel leakage. The behavior of back channel leakage is confirmed by the OTFT saturated-regime drain-current formula multiplied by channel length. For dual gate OTFT devices, a top gate voltage sweep and fixed different bottom gate voltages are applied, which indicates that the conduction path is distributed throughout the entire organic semiconductor (OSC) layer, and the back channel leakage can be suppressed by a positive bottom gate voltage. Finally, using dual gate sweeping for a dual gate OTFT device allows the top and bottom gate voltage to simultaneously control the front and back channels, causing a suppression of the back channel leakage, an improvement in subthreshold swing (SS) from 420 to 200 (mV/decade) and an on current increase from $\textsf {7.8}\times \textsf {10}^{-\textsf {8}}$ to $\textsf {3.3}\times \textsf {10}^{-\textsf {7}}$ A at VG-Vsub-threshold = −8 V for the W/L $=50/20~\mu \text{m}$ device.

Simulation of the effect of parasitic channel height on characteristics of stacked gate-all-around nanosheet FET

By using technology computer aided design (TCAD) simulation, the aim of this paper is to investigate the effect of Si parasitic channel, which is placed under stacked nanosheet channels, on electrical characteristic of stacked nanosheet GAA FETs. We have controlled the parasitic channel height, and evaluated the effect on electrical performance of the device. Trade-off in performance of the nanosheet FET is observed: the increase in parasitic channel height results in improvement in subthreshold swing and on/off ratio, while the increase in capacitance brings worse RC delay and active power. The parasitic channel height control in devices with ground plane doping is also investigated.

A Novel Negative Capacitance Tunnel FET With Improved Subthreshold Swing and Nearly Non-Hysteresis Through Hybrid Modulation

In this letter, a novel negative capacitance tunnel FET (NC-TFET) design based on junction depleted-modulation is proposed and experimentally demonstrated with sub-60mV/dec subthreshold swing (SS). By a striped gate stack design with integrated ferroelectric Hf0.5Zr0.5O2, the fabricated Si NC junction-modulated TFET (NC-JTFET) exhibits steeper SS, higher ON-current for almost two decades than Si TFET without OFF-current degradation, as well as nearly non-hysteresis behavior. The experimental results show the great potential of NC-JTFET for ultralow-standby-power IoT applications.

Impact of Semiconductor Permittivity Reduction on Electrical Characteristics of Nanoscale MOSFETs

The dielectric screening property of a semiconductor is very crucial for the electrical characteristics of a MOSFET, and which can be described mathematically by Poisson equation via the permittivity. While the theory and experiments have corroborated the permittivity reduction of nanoscale Si, this paper studies the electrical characteristics of MOSFETs considering the reduced channel permittivity by quantum transport simulations. It is found that the channel permittivity reduction may mitigate the short-channel effects, showing subthreshold swing improvement and threshold voltage shift of MOSFETs in nanoscale. Compared to quantization effects, the positive and negative impacts of the channel permittivity reduction on the devices in particularly nanoscale have been investigated. This paper elucidates the necessity of considering semiconductor permittivity reduction for nanoscale device design and simulations.

Gate Field Plate Structure for Subthreshold Swing Improvement of Si Line-Tunneling FETs

Tunnel field-effect transistors (TFETs) are promising for use in ultralow-power applications owing to their distinct band-to-band tunneling operation. However, the ON-state current of these Si-based tunnel devices is considerably lower than that of MOSFETs. Furthermore, a high-κ dielectric is used as a gate insulator or spacer to increase the TFET's tunneling field strength; this usually causes fringe-induced barrier lowering and deterioration of its subthreshold characteristics. Here, in this paper, a gate field plate TFET (GFP-TFET) structure is proposed to enhance the driving current and suppress the current kink induced by fringe-induced barrier lowering. A detailed investigation into the effects of a gate field plate on TFET performance was conducted with the help of extensive device simulations. The gate oxide and gate field plate oxide could be used to tailor the electric field lines to increase the electric field in the tunnel junction. Meanwhile, the fringing field concentration was reduced by using a metal with a relatively high work function as the field plate electrode. Thus, the electric field strength decreased near the gate edge and increased in the channel. The GFP-TFET exhibited high driving current and low subthreshold characteristics at the cost of a reduction in cutoff frequency. A GFP-TFET structure with optimized parameters had a 103× higher ON-state current compared with a normal silicon tunnel FET. The minimum subthreshold swing decreased from 146.3 to 21.4 mV/dec and the ON/OFF current ratio increased from 107 to 1013 compared with a normal TFET.

Optimization of III–V heterojunction tunnel FET with non-uniform channel thickness for performance enhancement and ambipolar leakage suppression

The optimized non-uniform channel thickness design for type-II and -III GaAs1−xSbx/In1−yGayAs heterojunction tunnel FETs (TFETs) is proposed for improving on currents (Ion) and suppressing ambipolar leakage. Quantum confinement induced bandgap widening as a function of channel thickness (Tch) is considered. For non-uniform Tch TFETs, the thick source/channel junction thickness (Ts) with small bandgap maintains small tunneling barrier and high Ion, while the thin drain/channel junction thickness (Td) with large bandgap reduces the ambipolar leakage. With the same Ioff, type-II non-uniform TFET exhibits 4 times higher Ion (238 µA/µm) than the type-II uniform TFET, and type-III non-uniform TFET shows 63% improvement in Ion (538 µA/µm) compared with the type-III uniform TFET. The optimized non-uniform type-II TFET (GaAs0.4Sb0.6/In0.65Ga0.35As) is designed with Ts ≥ 9 nm and Td = 4–5 nm, and the optimized non-uniform type-III (GaAs0.1Sb0.9/InAs) TFET is designed with Ts = 8–9 nm and Td = 4–5 nm. The Ioff of non-uniform Tch TFETs can be further suppressed as Td scales down to below 3 nm. However, Ion degradation is observed for non-uniform Tch TFETs with thin Td ≤ 3 nm due to extra energy barrier. The Ioff of type-III non-uniform TFETs can be further reduced by using gate-to-drain underlap design. Compared with the conventional TFETs with uniform Tch, the non-uniform Tch TFETs exhibit significant improvement in subthreshold swing, which benefits ultra-low power applications.

Improved Subthreshold Swing and Short Channel Effect in FDSOI n-Channel Negative Capacitance Field Effect Transistors

Negative capacitance (NC) FETs with channel lengths from 30 nm to $50~\mu \text{m}$ , gated with ferroelectric hafnium zirconium oxide are fabricated on fully depleted silicon-on-insulator (FDSOI) substrates. Enhanced capacitance due to NC, hysteresis-free operation, and improved subthreshold slope are observed. The NC effect leads to enhancement of drain current for small voltage operation. In addition, improved short channel performance is demonstrated owing to the reverse drain induced barrier lowering characteristics of the NC operation.

On the Electrical Characteristics of Ferroelectric FinFET Using Hafnium Zirconium Oxide with Optimized Gate Stack

We investigated a short-channel ferroelectric FinFET using a ferroelectric HfZrO thin film as gate dielectrics, and scaled down the channel length to 60 nm to study the short-channel effect and the ferroelectricity. The HfZrO FinFETs exhibited improved short-channel performance including subthreshold swing improvement and reduced drain-induced barrier lowering effect. By using pulsed I–V measurement method, we confirmed that the thickness tradeoff between HfZrO ferroelectric layer and buffered layer are critical to alleviate the influence of interface traps and simultaneously obtain the ferroelectricity in HfZrO FinFET devices with the consideration of sidewall traps. Interface traps may cause unwanted off-state leakage current and mismatching negative capacitance. Here, we demonstrated that the ferroelectric behavior can be achieved by simultaneously increasing HfZrO thickness to obtain the optimized polarization and adopt appropriate buffered layer to screen the traps effect under ferroelectric domain switching.

Characterization of Scaling in Ultra-Thin Poly-Si and Analysis of the Scaling Limit of Thin Film Thickness

Ultra-thin poly-Si channel has been widely studied and has already been adopted commercially by semiconductor manufacturers due to its short channel effect suppression and sub-threshold swing improvement. It is well known that the threshold voltage, VTH, increase as the poly-Si thickness, ts, is scaled below 10nm, due to quantum-mechanical (QM) effects. Although experiment results of VTH demonstrated identical behavior of increasing as ts was scaled, but the measured absolute VTH show significantly larger value than the expectation. The major problem of abrupt VTH increase is that it degenerate VTH distribution, which would cancel out merits of ultra-thin poly-Si device on high speed performance. Simulation results show the abrupt VTH increase is caused by a combined effect of bulk and front/back interface trap charges. As scaled down, yet the bulk trap density decrease, VTH is increased as it is overturned by front and back interface trap charge effects. Compared to front interface trap charges, back interface trap charges have larger influence on VTH. Since device with ts below 10nm is fully depleted before the gate voltage reaches VTH, the additional electric field formed across the poly-Si channel parallel shifts the band downwards. So the more parallel shifted the band is, the more additional portion of the front and back interface is filled with negative charge. As a result back interface charges increase VTH. The closer it gets to the channel, greater the influence become. It is quite clear why back interface trap charges contribute more to the VTH, compared with front interface trap charges. The simulation results considering bulk and front/back interface trap effects showed a good match experiment results. Considering the abrupt VTH increase and variation of poly-Si deposition process, the fundamental criterion of poly-Si thickness scaling limit should be no lower than 5nm.

Tunable electrical properties of multilayer HfSe2 field effect transistors by oxygen plasma treatment.

HfSe2 field effect transistors are systematically studied in order to selectively tune their electrical properties by optimizing layer thickness and oxygen plasma treatment. The optimized plasma-treated HfSe2 field effect transistors showed a high on/off ratio improvement of four orders of magnitude, from 27 to 105, a field effect mobility increase from 2.16 to 3.04 cm2 V-1 s-1, a subthreshold swing improvement from 30.6 to 4.8 V dec-1, and a positive threshold voltage shift between depletion mode and enhancement mode, from -7.02 to 11.5 V. The plasma-treated HfSe2 photodetector also demonstrates a reasonable photoresponsivity from the visible to the near-infrared region of light.

Subthreshold swing improvement in MoS2 transistors by the negative-capacitance effect in a ferroelectric Al-doped-HfO2/HfO2 gate dielectric stack

Obtaining a subthreshold swing (SS) below the thermionic limit of 60 mV dec-1 by exploiting the negative-capacitance (NC) effect in ferroelectric (FE) materials is a novel effective technique to allow the reduction of the supply voltage and power consumption in field effect transistors (FETs). At the same time, two-dimensional layered semiconductors, such as molybdenum disulfide (MoS2), have been shown to be promising candidates to replace silicon MOSFETs in sub-5 nm-channel technology nodes. In this paper, we demonstrate NC MoS2 FETs by incorporating a ferroelectric Al-doped HfO2 (Al : HfO2), a technologically compatible material, in the FET gate stack. Al : HfO2 thin films were deposited on Si wafers by atomic layer deposition. Voltage amplification up to 1.25 times was observed in a FE bilayer stack of Al : HfO2/HfO2 with a Ni metallic intermediate layer. The minimum SS (SSmin) of the NC-MoS2 FET built on the FE bilayer improved to 57 mV dec-1 at room temperature, compared with SSmin = 67 mV dec-1 for the MoS2 FET with only HfO2 as a gate dielectric.

Accurate analysis of top gate effect of a typical triple-gate fin-type FET using three-dimensional device simulation

Triple-gate (TG) fin-type FETs (FinFETs) are used in advanced mass production of high-performance devices. The TG FinFET was developed from the double-gate (DG) FinFET by adding another gate for higher performance and lower variability. We analyzed the effect of the top gate of a typical TG FinFET using three-dimensional (3D) device simulation accurately for the first time. It was found that the top gate improves the drain-induced barrier lowering (DIBL) by 9%. The improvements of the threshold voltage (Vth) and ON current (Ion) were found to be as small as 5 and 7%, respectively. The improvement of subthreshold swing (SS) was very small at 1% despite our expectation. However, the OFF current (Ioff) was substantially reduced by 28% contrary to our intuitive prediction. The top gate only slightly enhances the electrostatic controllability of the channel current, so the improvements of device performance are marginal except that it has a large effect on Ioff reduction. It is therefore found that the biggest role of the top gate of a typical TG FinFET is substantially decreasing Ioff. The reason for the Ioff reduction is the increase in the bottleneck energy of the conduction band near the channel surface by 100 meV caused by the presence of the top gate. Since the large Ioff reduction is very important to suppress power consumption, our new knowledge is beneficial to develop ultralow-power devices.