Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes

Abstract

In this paper, for the first time, we have investigated the DC, analog/RF, and linearity metrics of asymmetric spacer junctionless (JL) Gate-All-Around (GAA) vertically stacked nanowire field-effect-transistor (FET) for significantly enhanced performance at sub-5 nm nodes. The symmetric and asymmetric spacer lengths are optimized and compared towards the improvement of subthreshold swing (SS) and switching (IONIOFF) behavior with various spacer dielectrics. For optimal values of source (LS) and drain (LD) spacer lengths, the device IONIOFF ratio has an improvement of 22.69% and a reduction in IOFF by 34.13% as compared to other variations. Our study reveals that, in symmetric spacer variations the device exhibits superior performance with LS=LD=1.5×LG. However, compared to symmetric, the asymmetric spacer exhibits higher IONIOFF and lower SS with LS=1.5×LG and LD=2.5×LG. Moreover, LG scaling impact on SS, DIBL, Vth, and ION are reported with various spacers. The optimized asymmetric spacer exhibits excellent DC characteristics with SS of 64 mV/dec and IONIOFF ratio of ∼108 even for 5 nm gate length (LG) ensures fundamental scaling. At LG of 10 nm with asymmetric spacer, a cut-off frequency (fT) = 0.4 THz, gain-bandwidth product (GBW) = 0.08 THz, and intrinsic delay (τ) = 1.3 ps are achieved. Finally, the device exhibits second order harmonic (gm2) = 0.2 mA/V2 and third order harmonic (gm3) = 1.1 mA/V3 at nano-regime. Thus optimally designed JL nanowire FET ensures potential candidate towards low-power, high frequency, and better linearity for future technology nodes.