Accurate analysis of top gate effect of a typical triple-gate fin-type FET using three-dimensional device simulation

Abstract

Triple-gate (TG) fin-type FETs (FinFETs) are used in advanced mass production of high-performance devices. The TG FinFET was developed from the double-gate (DG) FinFET by adding another gate for higher performance and lower variability. We analyzed the effect of the top gate of a typical TG FinFET using three-dimensional (3D) device simulation accurately for the first time. It was found that the top gate improves the drain-induced barrier lowering (DIBL) by 9%. The improvements of the threshold voltage (Vth) and ON current (Ion) were found to be as small as 5 and 7%, respectively. The improvement of subthreshold swing (SS) was very small at 1% despite our expectation. However, the OFF current (Ioff) was substantially reduced by 28% contrary to our intuitive prediction. The top gate only slightly enhances the electrostatic controllability of the channel current, so the improvements of device performance are marginal except that it has a large effect on Ioff reduction. It is therefore found that the biggest role of the top gate of a typical TG FinFET is substantially decreasing Ioff. The reason for the Ioff reduction is the increase in the bottleneck energy of the conduction band near the channel surface by 100 meV caused by the presence of the top gate. Since the large Ioff reduction is very important to suppress power consumption, our new knowledge is beneficial to develop ultralow-power devices.