Improvement In Short Channel Effects Research Articles

Impact of Al2O3 spacers on the improvement in short-channel effects for the mesa-shaped vertical-channel In-Ga-Zn-O thin-film transistors with a channel length below 100 nm

To achieve a channel length scaling and an improvement in short-channel effect (SCE) for the mesa-shaped vertical thin-film transistors (VTFTs) using In-Ga-Zn-O (IGZO) channels prepared by atomic layer deposition (ALD), the impacts of two strategic approaches were investigated: the introduction of an ALD Al2O3 spacer and the modulation of ALD oxidants. The Al2O3 spacers were patterned with sound profiles by means of a hybrid-etching technique combining a wet- and plasma dry-etching processes to form vertical sidewalls corresponding to a channel length. For the cases when the Al2O3 spacers were prepared with H2O oxidant, the IGZO VTFT with an In/Ga ratio of 1.7 showed the degradations in device characteristics including a turn-on voltage (VON) of −8.0 V and a subthreshold swing (SS) of 1.50 V/dec. When the In/Ga ratio was increased to 2.9, the device failed to be operated with conductive properties. The excess hydrogen contained within the Al2O3 spacer was suggested to be thermally diffused into the IGZO from the back-channel interface, leading to marked increase in the number of conduction carriers within the channel. To suppress the doping effect of hydrogen from the spacer, the ALD oxidant was strategically modulated to O3. As results, the VON and SS of the IGZO VTFT were markedly improved to be −2.0 V and 0.483 V/dec, respectively. Additionally, the drain induced barrier lowering coefficient was also significantly enhanced from 2.9 to 0.13 V/V, demonstrating the excellent immunity against the SCE for the IGZO VTFTs with nanoscale channel lengths. It was concluded from these findings that the spacer engineering can be one of the most important guides for the implementation of IGZO VTFTs with channel lengths below 100 nm.

Improvement in Short-Channel Effects and Bias-Stress Stability of Vertical Thin-Film Transistors Using Atomic-Layer-Deposited In–Ga–Sn–O Channels

Improvement in Short-Channel Effects and Bias-Stress Stability of Vertical Thin-Film Transistors Using Atomic-Layer-Deposited In–Ga–Sn–O Channels

Improvement in Short-Channel Effects of the Thin-Film Transistors Using Atomic-Layer Deposited In–Ga–Sn–O Channels With Various Channel Compositions

In–Ga–Sn–O (IGTO) thin-film transistors (TFTs) were fabricated with channel lengths from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3 \mu \text{m}$ </tex-math></inline-formula> to 500 nm to investigate the short-channel effects (SCEs), in which IGTO channel compositions were modulated during the atomic-layer deposition. The SCEs appearing in the IGTO TFTs were found to be manifested by increasing the In/Ga ratio of IGTO channel, showing typical channel composition dependence. Alternatively, small values of the channel-length reduction and contact resistance could be obtained to be 50 nm and 0.52 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{k}\Omega $ </tex-math></inline-formula> , respectively, for the device using the IGTO channel with an In/Ga ratio of 1.7. Threshold voltage shifts of the IGTO TFT were estimated to be only +0.03 and +1.22 V under negative and positive gate-bias stress for 104 s, respectively, even with a channel length as short as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1 \mu \text{m}$ </tex-math></inline-formula> .

Performance Analysis of Vertically Stacked Nanosheet Tunnel Field Effect Transistor with Ideal Subthreshold Swing

In this paper, a novel vertically stacked silicon Nanosheet Tunnel Field Effect Transistor (NS-TFET) device scaled to a gate length of 12 nm with Contact poly pitch (CPP) of 48 nm is simulated. NS-TFET device is investigated for its electrostatics characteristics using technology computer-aided design (TCAD) simulator. The inter-band tunneling mechanism with a P-I-N layout has been incorporated in the stacked nanosheet devices. The asymmetric design technique for doping has been used for optimum results. NS-TFET provides a low leakage current of order10−16 A, an excellent subthreshold swing (SW) of 23mv/decade, and negligible drain induced barrier lowering (DIBL) having a value of 10.5 mv/V. The notable ON to OFF current ratio of the order of 1011 has been achieved. The device exhibits a high transconductance of 3.022 × 10−5 S at the gate to source voltage of 1 V. The radiation effect of an alpha particle at different energies on NS-TFET is investigated. The injection causes drain current fluctuation for a short span and the result can serve as a guideline for designing of a robust circuit. NS-TFET shows tremendous improvement in short channel effects (SCE) and is a good option for advanced technologies.

A Model for Gate-Underlap-Dependent Short- Channel Effects in Junctionless MOSFET

In this paper, we investigate the impact of gate–source/drain underlap on short-channel behavior of junctionless (JL) transistor through a quasi-analytical model and 2-D numerical simulations. The proposed five-region model for potential is developed for the symmetric mode operation of double-gate (DG) JL MOSFET in the subthreshold regime, to predict and minimize short-channel effects (SCEs) using the optimum design of underlap regions. The five-region model can be transformed into four or three regions to incorporate the possible dependence of biases, doping, and gate workfunction with the underlap length. The parameters indicating SCEs can also be extracted using an analytical approximation for subthreshold drain current. The results from the proposed model are in reasonable agreement with simulation data. Analyses show that underlap length is a critical parameter to restrict the lateral extension of depletion region into the ungated portion. With increasing the underlap length, SCEs improve prominently for moderate doping concentration ( $10^{18}$ cm $^{-3}$ ). The improvement in SCEs ceases once the device achieves the maximum lateral extension of the depletion region. This paper provides the physical insights into the optimal use of underlap region in nanoscale JL devices for suppressing SCEs.

Design and Simulation of Nanoscale Double Gate MOSFET using high K Material and Ballistic Transport Method

The Phenomenal scaling of MOSFET helps in sustaining of Moore’s law and also helped in improving the performance. As per the 2009 ITRS projection document the channel length will go down to 12nm approximately by 2020 and moving beyond the 50nm technology conventional MOSFET technology needs advancement to overcome the restrictions imposed by fundamental Physics [1] such as tunnelling of charge carriers through gate oxide, increased leakage current. Reduction in leakage current and short channel effects can be achieved using high K dielectric material. Double gate MOSFET is another possible solution as multiple gates devices improves the circuit performance like improvement in the short channel effects because of better charge control, faster circuit speed because of increased current. Improvement of short channel effects in Double gate MOSFET allows additional gate length scaling.

Performance analysis of SOI MOSFET with rectangular recessed channel

In this paper a two dimensional (2D) rectangular recessed channel–silicon on insulator metal oxide semiconductor field effect transistor (RRC-SOI MOSFET), using the concept of groove between source and drain regions, which is one of the channel engineering technique to suppress the short channel effect (SCE). This suppression is mainly due to corner potential barrier of the groove and the simulation is carried out by using ATLAS 2D device simulator. To have further improvement of SCE in RRC-SOI MOSFET, three more devices are designed by using dual material gate (DMG) and gate dielectric technique, which results in formation of devices i.e. DMRRC-SOI,MLSMRRC-SOI, MLDMRRC-SOI MOSFET. The effect of different structures of RRC-SOI on AC and RF parameters are investigated and the importance of these devices over RRC MOSFET regarding short channel effect is analyzed.

Capacitance modeling of gate material engineered cylindrical/surrounded gate MOSFETs for sensor applications

This paper presents charge based analytical drain current and capacitance model of material engineered Cylindrical/Surrounded Gate (CGT/SGT) MOSFET with nanogap cavity region for sensor applications. Material engineered i.e. dual material gate provides improvement in Short Channel Effects (SCEs) and cylindrical shape nanogap cavity region is used for sensing of biomolecule strength. The material engineered CGT/SGT MOSFET sensor electrically detect the targeted biomolecules of different strength by change in drain current and gate capacitance. Analysis has been carried out by using unified charge control based model derived from Poisson's equation. It is shown that sensitivity of changing biomolecules strength is more in gate capacitance than the drain current. The results so obtained are in good agreement with the 3D simulated data which validate the model.

Keynote; Material Challenges and Opportunities in Ge/III-V Channel MOSFETs

CMOS utilizing high mobility Ge/III-V channels on Si substrates is expected to be one of promising devices for high performance and low power logic LSIs in the future. There can be several CMOS structures using III-V/Ge channels. One of the ultimate CMOS can be the co-integration of a III-V nMOSFET and a Ge pMOSFET. While Ge or III-V CMOS is also plausible in terms of the simplicity of the material integration, the key issues are the realization of high performance Ge nMOSFETs or III-V pMOSFETs. Also, even in Ge pMOSFETs and III-V nMOSFETs, the CMOS technologies have not been established yet. Thus, viable CMOS structures using III-V and/or Ge channels are still strongly dependent on coming progress in the device/process/integration technologies.In addition, one of the most important issues for applying to the future technology nodes is suppression of short channel effects, which can be realized by ultrathin body (UTB) channels. Particularly, we would prefer planar UTB/UTBOX-based structures, which can realize further improvement of short channel effects by combination with multi-gate structures such as FinFET and Tri-gate/nanowire MOSFETs. This scheme allows us to provide static and/or dynamic Vth control through UTBOX by Si substrate doping and back bias under simple structures and fabrication processes. Here, the difficult challenges for realizing high performance logic devices include the III-V/Ge ultrathin body channel formation, the low resistivity S/D formation, the mobility enhancement in such ultrathin body channels and superior MOS gate stacks. Our approach for the channel formation is the wafer bonding for III-V materials and the Ge condensation technique for Ge/SiGe channels. Also, metal S/D technologies are regarded as promising for reducing parasitic S/D resistance. In order to maintain high channel mobility, we employ optimized channel design of quantum wells (QW) with MOS interface buffers for III-V channels, and surface orientation and strain engineering for Ge channels. The GeOx-based gate stacks are important for obtaining high mobility Ge MOSFETs with ultrathin EOT. We have proposed and demonstrated UTB InGaAs-based channel formation for III-V nMOSFETs by using direct wafer bonding. Ultrathin body (3.2 nm InGaAs)/UTBOX (Al2O3(4.4 nm)/SiO2(3.3 nm)) substrates are realized with high material quality. As channel engineering to boost the mobility in UTB InGaAs-based channels, we have introduced two boosters, higher In content InAs channels and MOS interface buffers composed of lower-In-content buffers. Based on these technologies, we have realized sub-20-nm-channel-length Tri-gate InGaAs/InAs/InGaAs-OI QW MOSFETs with good electrostatic. Here, wide-range Vth tunability in Tri-gate InAs-OI MOSFETs through VB control has been demonstrated. As for III-V pMOSFETs, we have also demonstrated UTB GaSb-OI pMOSFETs on Si by using wafer bonding. Based on these technologies, a novel III-V CMOS structure composed of GaSb/InAs hetero-structures is proposed.One of the most critical issues in Ge MOSFETs is the realization of gates stacks with superior MOS interfaces. In order to realize low Dit, high mobility and thin EOT at the same time, we have proposed a interfacial layer formation process employing ECR oxygen plasma to form GeOx ILs after thin Al2O3 or HfO2/Al2O3 ALD. This ultrathin GeOx IL is found to effectively reduce Dit in both valence and conduction band sides. N- and p-MOSFETs with the HfO2/Al2O3/GeOx/Ge gate stacks exhibit the excellent electrical characteristics under EOT of 0.76 nm. In spite of this ultrathin EOT, high electron and hole mobility is obtained in comparison with the thick GeO2/Ge mobility and the Si mobility, particularly in high Ns region. These results strongly demonstrate that HfO2/Al2O3/GeOx/Ge gate stacks can realize high performance Ge n- and pMOSFETs with minimal mobility expense under aggressive scaling of EOT.

A Comparison of Short-Channel Control in Planar Bulk and Fully Depleted Devices

The short-channel effects (SCEs) of planar bulk and fully depleted finFET devices have been compared using the same junction overlap and lateral gradient, and it is shown that, for finFET devices, a significant component of electrostatic control arises from a naturally present shallow extension junction. When such shallow junctions are applied to a bulk device, we show that the SCE becomes comparable to that of a finFET. Furthermore, we show that, if an embedded source/drain stressor is incorporated in a bulk device, it will not degrade the short-channel benefit of the ultrashallow junctions. The ability to span a wide power/performance range by doping and the improvement in SCEs by the use of ultrashallow extension junctions can potentially extend the life of bulk-type technologies.

Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme

In this paper, characteristics of the 2-bit recessed channel memory with lifted-charge trapping nodes are investigated. The length between the charge trapping nodes through channel, which is defined as the effective memory node length (Meff), is extended by lifting up them. The dependence of VTH window and short channel effect (SCE) on the recessed depth is analyzed. Improvement of short channel effect is achieved because the recessed channel structure increases the effective channel length (Leff). Moreover, this device shows highly scalable memory characteristics without suffering from the bottom-side effect (BSE).

Improved Electrical Characteristics of Ge-on-Si Field-Effect Transistors With Controlled Ge Epitaxial Layer Thickness on Si Substrates

The authors report on the novel MOSFETs that were fabricated on thin relaxed Ge epitaxial layers grown on Si substrates. With controlled epi-Ge thickness, selectively activated shallow source/drain (S/D) junctions are formed using low dopant activation energy of Ge. The Ge epitaxial layers determine the effective S/D junction depth by selectively activating S/D implantations only in the Ge layers, while suppressing activation in the Si substrates. Low junction leakage current and capacitance are also achieved by forming S/D junctions in Si substrates as well as in Ge layers with controlled epi-Ge thickness. With this technique applied to Ge-on-Si epitaxial layers, Ge pMOSFETs showed an improvement in short channel effects and junction characteristics.

Germanium &amp; Carbon Co-implantation for Enhanced Short Channel Effect Control in PMOS Devices

AbstractThis work demonstrates the efficiency of a Germanium and Carbon co-implantation that suppresses the Boron Transient Enhanced Diffusion, enhances Boron activation and enables large improvement of Short Channel Effects in PMOS devices while maintaining drive current performances. We present here 65/45nm node devices on conventional bulk substrates featuring Germanium and Carbon engineered shallow junctions that enable to reduce the Drain Induced Barrier Lowering compared to devices implanted only with Boron. This improvement is attributed to the suppression of Boron channelling with Ge pre-amorphization (PAI), and to the reduction of Boron TED due to the trapping of interstitial defects by Carbon with Germanium PAI.

Double pocket architecture using indium and boron for sub-100 nm MOSFETs

A double pocket architecture for sub-100 nm MOSFET's is proposed on the basis of indium pocket profiling at higher dose than the amorphization threshold. At high dose, the low-energy indium pockets realize the improvement of short channel effects and shallow extension formation of a highly doped drain, maintaining the low junction leakage level. A double pocket architecture using indium and boron is demonstrated in a 70 nm gate length MOSFET with high drive currents and good control of the short channel effects.

The improvement of short-channel effects due to oxidation-induced boron redistribution for counter-implantation p-MOSFET's

Delayed appearance of short-channel effects in the threshold voltage falloff has been observed for counterimplantation p-MOSFETs. The phenomenon is attributed to the oxidation-induced boron redistribution along the channel. SUPREM-3 and MINIMOS-5 and the Orlowski method were used to quantitatively characterize this behavior. Quite good agreement between simulation and experimental data were obtained. It was found that the device characteristics of submicrometer counterimplanted p-MOSFETs are improved due to the effects of boron redistribution near the channel edge.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Hot-carrier reliability in double-implanted lightly doped drain devices for advanced drams

Hot-electron degradation in short-channel (0.50 μm and 0.83 μm) double-implanted lightly doped drain (DI-LDD) devices was characterised using DC stress tests. Compared to lightly doped drain (LDD) devices of the same effective channel length Leff, the measurements indicate that channel hot-electron injection is more prevalent in devices with the p+-pocket implant due to a higher peak channel electric field. Degradation is more severe in both the drain current and transconductance. However, an improvement in shortchannel effects was seen in DI-LDD devices over LDD devices. For the same Leff, the punch-through voltage was higher and the subthreshold swing lower for the DI-LDD devices.