A Model for Gate-Underlap-Dependent Short- Channel Effects in Junctionless MOSFET

Abstract

In this paper, we investigate the impact of gate–source/drain underlap on short-channel behavior of junctionless (JL) transistor through a quasi-analytical model and 2-D numerical simulations. The proposed five-region model for potential is developed for the symmetric mode operation of double-gate (DG) JL MOSFET in the subthreshold regime, to predict and minimize short-channel effects (SCEs) using the optimum design of underlap regions. The five-region model can be transformed into four or three regions to incorporate the possible dependence of biases, doping, and gate workfunction with the underlap length. The parameters indicating SCEs can also be extracted using an analytical approximation for subthreshold drain current. The results from the proposed model are in reasonable agreement with simulation data. Analyses show that underlap length is a critical parameter to restrict the lateral extension of depletion region into the ungated portion. With increasing the underlap length, SCEs improve prominently for moderate doping concentration ( $10^{18}$ cm $^{-3}$ ). The improvement in SCEs ceases once the device achieves the maximum lateral extension of the depletion region. This paper provides the physical insights into the optimal use of underlap region in nanoscale JL devices for suppressing SCEs.