Performance enhancement and supression of short channel effects of 14nm double gate FETs by using gate stacked high-k dielectrics & workfunction variation

Abstract

Double-gate (DG) MOSFETs became popular due to its excellent scalability and better immunity to short Channel Effects. They are used for CMOS applications beyond the 70 nm node of the ITRS roadmap. However DG devices with channel lengths below 100nm show considerable leakage current and threshold voltage roll off. In this paper, we propose and validate a novel design for a double-gate field-effect transistor (DG FET) with 14nm gate length. Impact of high-k dielectrics along with and without gate stacking with 0.5nm EOT and work function variation on Short Channel Effects (SCEs) is studied using visual TCAD 2-D. Effect of Variation of interfacial thickness layer in gate stack on SCEs is also observed. Tradeoff between threshold voltage and SCEs is observed in work function analysis. Improvement in SCEs is observed with work function optimization. I on /I off ratio is observed for different work function values. Finally, optimized range for work function values is discussed for better suppression of SCEs.