Impact Of Process Variations Research Articles

Mismatch of Ferroelectric Film on Negative Capacitance FETs Performance

In this article, we analyze the impact of process variations of the ferroelectric film on the performance of the negative capacitance field-effect transistor (NCFET). Variations of the ferroelectric layer area (resulting from the variation of the transistor dimension sizes and the edge-effect), the ferroelectric layer thickness, the polarization, and the coercivity are taken into consideration to evaluate the impact on the NCFET performance. These results can serve as a guideline to improve both the circuit performance and yield for analog and digital circuits. To showcase this ability, the influence of these variations on the oscillating frequency of a five-stage ring oscillator and the mirroring current of a current mirror are analyzed. The results show that the distribution of the standard derivation of the oscillating frequency is 1.9 MHz on condition of ${T}_{\text {FE}}={14}$ nm, ${W}_{\text {P}}/{L}_{\text {P}}={1}~\mu \text{m}$ /45 nm, and ${W}_{\text {N}}/{L}_{\text {N}}={500}$ /45 nm, and the standard derivation of the mirroring current is $0.17~\mu \text{A}$ on condition of ${W}={1}\,\,\mu \text{m}$ , ${L}={500}$ nm, and ${T}_{\text {FE}}={20}$ nm.

Impact of process variability in junctionless FinFETs due to random dopant fluctuation, gate work function variation, and oxide thickness variation

In this paper, process variability such as random dopant fluctuation (RDF), work function variation (WFV), and oxide thickness variation (OTV) in 14 nm node junctionless (JL) FinFETs is investigated using the impedance field method (IFM). Effects of doping concentration, gate metal grain-related parameters, and device parameter scaling on RDF, WFV, and OTV induced variability are studied using the standard deviations of threshold voltage (σVth) and subthreshold slope (σSsub). As a result, we find that a relatively low doping concentration helps alleviate process variability. As average grain size increases, different mechanisms of σVth and σSsub degradation are analyzed for WFV and OTV induced variability. Compared to WFV and OTV, RDF is revealed as the most significant source of variability as devices scale down. It is observed that fin width (Wfin) and oxide thickness (tox) scaling leads to the reduction of RDF induced variability, whereas channel length (L) and fin height (Hfin) scaling results in aggravation of RDF, WFV, and OTV induced variability.

PREPARATION OF ORAL CURCUMIN DELIVERY FROM 3D-NANO-CELLULOSE NETWORKS MATERIAL PRODUCED BY ACETOBACTER XYLINUM USING OPTIMIZATION TECHNIQUE

Objective: To prepare oral curcumin delivery and optimize curcumin loading of 3D-nano-cellulose networks material (3DCM) by looking into the impact of process variables on the response utilizing response surface methodology (RSM) and Box-Behnken design.
 Methods: Optimization of curcumin loading of 3DCM was conducted using RSM and Box-Behnken model. Impact of four independent variables, including, the concentration of curcumin (X1), temperature (X2), shaking speed (X3), and time of loading (X4), was studied on one dependent response, that is, an amount of loaded curcumin (Y). Characterization of optimized 3DCM including curcumin was examined by Scanning Electron Microscopy (SEM) and Fourier Transform Infrared (FTIR) analysis .
 Results: R2 value for Y was approximately 0.94. X1 possessed the biggest positive impact compared to X2, X3 and X4. Optimized conditions for curcumin loading of 3DCM were X1 at 3 mg/ml, X2 at 40 °C, X3 at 120 rpm and X4 at 120 min. SEM photograph of 3DCM surfaces were found including fibers creating a 3D network structure. FTIR spectra studies depicted that there was no interaction between curcumin and 3DCM.
 Conclusion: The data obtained in this study thus suggest that curcumin loaded 3DCM was successfully fabricated to give a potential oral delivery system of curcumin.

Enhancing Programming Variability in Multi-Bit Phase Change Memory Cells for Security

We performed gradual programming of phase change memory (PCM) line cells with repeated pulses to transition from the crystalline to the amorphous state through various intermediate states and analyzed the variability in programming trends for different cell shapes and sizes. The crystalline PCM cells experienced sequences of repeated applied voltage pulses of either identical amplitudes or gradually increasing amplitudes. With repeated identical amplitude pulses, large number of pulses (~1,000) were required to reach a full reset of the cells through partial reset and partial set steps. With repeated increasing amplitude pulses, ~20-30 pulses were sufficient to fully reset the cells through gradual partial reset steps. Both programming approaches resulted in significant cell-to-cell variability for all cells, with stronger variability for narrower cells. However, the latter pulsing approach was more practical and resulted in more uniform distribution of all states. The stronger cell-to-cell programming variability for the narrower cells is attributed to the smaller number of crystalline grains in each cell and to the larger relative impact of manufacturing process variations. Statistical analysis of two example data sets shows promise of PCM programming variability for hardware security applications.

An Energy-Efficient and High Throughput in-Memory Computing Bit-Cell With Excellent Robustness Under Process Variations for Binary Neural Network

In-memory computing (IMC) is a promising approach for energy cost reduction due to data movement between memory and processor for running data-intensive deep learning applications on the computing systems. Together with Binary Neural Network (BNN), IMC provides a viable solution for running deep neural networks at the edge devices with stringent memory and energy constraints. In this paper, we propose a novel 10T bit-cell with a back-end-of-line (BEOL) metal-oxide-metal (MOM) capacitor laid on pitch for in-memory computing. Our IMC bit-cell, when arranged in a memory array, performs binary convolution (XNOR followed by Bit-count operations) and binary activation generation operations. We show, when binary layers of BNN are mapped into our IMC arrays for MNIST digit classification, 98.75% accuracy with energy efficiency of 2193 TOPS/W and throughput of 22857 GOPS can be obtained. We determine the memory array size considering the word-line and bit-line nonidealities and show how these impact classification accuracy. We analyze the impact of process variations on classification accuracy and show how word-line pulse tunability provided by our design can be used to improve the robustness of classification under process variations.

Using yield to predict long-term reliability of integrated circuits: Application of Boltzmann-Arrhenius-Zhurkov model

Modified Boltzmann-Arrhenius-Zhurkov (BAZ) constitutive model is applied to predict the reliability of integrated circuits. The model accounts for the impact of physical defects and process variations on the stress-free activation energy, which is viewed as a critical material's property. It is shown that the probability of non-failure (reliability) and the corresponding mean-time-to-failure (MTTF) can be evaluated from the failure-oriented-accelerated-testing (FOAT) geared to the modified BAZ model. The general concept is illustrated by the experimental data.

Si metasurface half-wave plates demonstrated on a 12-inch CMOS platform

Abstract Half-wave plate (HWP) is one of the key polarization controlling devices in optical systems. The conventional HWPs based on birefringent crystals are inherently bulky and difficult to be monolithically integrated with other optical components. In this work, metasurface-based HWPs with high compactness are demonstrated on a 12-inch silicon complementary metal-oxide-semiconductor platform. Three-dimensional finite difference time domain simulation is used to design the nanostructure and investigate the impact of fabrication process variation on the device performance. In addition, the cross- and co-polarization transmittance (T cross and T co) of the HWPs located at different wafer locations are characterized experimentally. The peak T cross and valley T co values of 0.69 ± 0.053 and 0.032 ± 0.005 are realized at the wavelength around 1.7 μm, respectively. This corresponds to a polarization conversion efficiency of 95.6% ± 0.8%.

A novel area efficient on-chip RO-Sensor for recycled IC detection

Out of different types of counterfeit integrated circuits (ICs) present in the supply chain, recycled ICs are major threat to security and reliability of electronic components. Recycled ICs possess shorter lifetime and it is extremely difficult to distinguish a recycled IC in a group of fresh IC with similar functionality. Out of several recycled IC detection methodology, Ring Oscillator (RO) sensor based detection approach is most efficient, because of its simple design and can detect ICs used only for few days. In this paper, we proposed two different types of modified RO sensor with lower area overhead. First RO sensor accelerates the aging to improve the detection of recycled ICs which are used for few days. The second architecture uses current controlled configurable RO (C-CRO) to further improve the detection of recycled IC. The RO in both the proposed sensor is designed by using modified pseudo NMOS logic based inverter. The proposed inverter accelerates the aging caused by negative bias temperature instability (NBTI) and lower the impact of process variation (PV) to improve the rate of detection. Both the proposed RO sensors are simulated in 90 nm CMOS technology. The simulation result shows both the proposed sensor improves the rate of detection as compared to the conventional sensor.

Lead bioremoval from milk by Saccharomyces cerevisiae

The present study refers to the application of Saccharomyces cerevisiae for bioremoval of lead from milk, the most important dairy product. First, the impact of process variables on lead bioremoval by S. cerevisiae has been studied by Plackett-Burman Design. Then, the optimization of bioremoval process was carried out by three main factors; contact time, biomass and initial heavy metal concentration by using a central composite design. The analysis of variance showed that the models were highly significant. The model also described that lead bioremoval from milk is affected by all three factors. The optimized bioremoval was achieved after 4 days with 22 × 108 CFU inoculation of yeast in milk containing 70 μg/l of lead concentration. The reconfirmation test indicated that in the above mentioned optimum condition the highest yield of lead bioremoval was achieved at 70%. 3D plots analysis represented dual interaction effects on metal bioremoval. This study showed that S. cerevisiae is a natural potential biosorbent for lead bioremoval from milk. This approach could be also considered as a green technology useful in eliminating the heavy metal contaminations of drinking water and foodstuff.

Characterization of Half-Select Free Write Assist 9T SRAM Cell

Modern biomedical applications have created a high demand for low power static random access memory (SRAM). In this article, a reliable low power half-select free-write assist 9T (HFWA9T) cell has been proposed. To analyze the impact of process variations on different design metrics, the proposed cell has been compared with other contemporary designs such as feedback-cutting 7T (7T), fully differential 8T (FD8T), and single-ended disturb free 9T (SEDF9T) cells. The HFWA9T cell exhibits 2.87×/3.37× higher read stability or read static noise margin (RSNM) than that of 7T/FD8T and 1.40×/6.55× higher write ability or write static noise margin (WSNM) than that of FD8T/SEDF9T,2.90×/2.67× and 1.06×/1.01×/5.05× narrower spread in RSNM and WSNM than that of 7T/FD8T and 7T/FD8T/ SEDF9T cells, respectively. In addition, it shows 1.11×/1.03× narrower spread in read delay (TRA) than that of FD8T/SEDF9T and 1.33× shorter TRA than that of SEDF9T cell. Furthermore, it consumes only 0.67×/0.31×/0.48× of the write power and 0.262×/0.605×/0.90× of the read power, respectively, consumed by 7T/FD8T/SEDF9T, while consuming 0.34×/0.96× of static power consumed by 7T/FD8T cell. For all these improvements, it incurs a penalty of 1.62×/1.78× in write delay (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">WA</sub> ) compared to 7T/SEDF9T and 1.58×/1.58× in T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RA</sub> compared to 7T/FD8T cell at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 700 mV.

Impact of Process Variations on Delay in Carbon Nanotube Based Bus Interconnects At Different Technology Nodes

This paper presents the impact of process variations in carbon nanotube based advanced bus interconnects such as single walled carbon nanotube (SWCNT), multi walled carbon nanotube (MWCNT) and mixed carbon nanotube bundle (MCB). The impact of temperature variations on paracitics of interconnects for variable interconnects at different technology nodes is analyzed. From the analysis, it reveal that the mixed bundle carbon nanotube offering the lower paracitics even higher temperatures compared to SWCNT and MWCNT which leads to lower delay and crosstalk effect when it is used in bus interconnects. Further we have also done delay analysis by changing the bundle area, number of shells and metallic ratio of three interconnect structures with the insertion of obtained parasitics using empirical formulas. It is proven that the mixed CNT (MCB) interconnect structures offered a lesser delay compared to other CNT interconnect structures. All the analysis has been done using MATLAB at 22nm and 32nm technology nodes.

Process Optimization and Implementation of Online Monitoring Process in the Transfer Molding for Electronic Packaging

Abstract The quality of molded packages heavily depends on the process parameters of the molding process and on the material characteristics of epoxy molding compounds (EMCs). When defects are introduced into the electronic packages in one of the last steps in the manufacturing process, namely, during encapsulation, it may cause high failure costs. To decrease the number of defects due to the molding process, a comprehensive understanding of the impact of process parameters and variations in the characteristics of the EMC on package quality is necessary. This study aimed at supporting a deeper understanding of the influence of process parameters and variations in the material characteristics of the EMC on package quality. A systematic approach was introduced to generate a process model describing the correlation between process parameters and package quality to obtain optimum process parameters for the transfer molding process. The influence of the alterations in material characteristics of the EMC due to prolonged storage duration and humidity on void formation and wire sweep was investigated. An online monitoring method, dielectric analysis (DEA), was implemented into the transfer molding process to monitor the variations in the cure behavior of the EMC. A second molding compound was used to analyze the similarities in the alteration behavior of the molding compounds when subjected to the same preconditioning and to generalize the characteristic information obtained from DEA.

Variability-aware cryogenic models of mosfets: validation and circuit design

In this paper, a metal–oxide–semiconductor-field-effect-transistor modeling methodology for cryogenic conditions has been extensively verified through device measurements performed on a cryogenic probe station that was cooled by liquid nitrogen (−196 °C). The approach is valid for all operating regions (including the sub-threshold mode). The developed model can estimate ID – VGS and ID–VDS curves of transistors having different channel lengths and widths with an error of less than 5%. Statistical analysis of cryogenic measurements is used to introduce the variation levels around the nominal cryogenic operation to identify the impact of process variations at cryogenic conditions. Models adjusted to various temperatures between −196 °C and −40 °C have been developed for applications requiring different cryogenic operation conditions. Experimental data collected from a ring oscillator is employed to visualize the model performance in estimating the cryogenic characteristics of a typical integrated circuit. It is shown that the frequency of the ring oscillator is correctly simulated using the proposed cryogenic models.

Variability aware FinFET SRAM cell with improved stability and power for low power applications

PurposeMajor area of a die is consumed in memory components. Almost 60-70% of chip area is being consumed by “Memory Circuits”. The dominant memory in this market is SRAM, even though the SRAM size is larger than embedded DRAM, as SRAM does not have yield issues and the cost is not high as compared to DRAM. At the same time, the other attractive feature for the SRAM is speed, and it can be used for low power applications. CMOS SRAM is the crucial component in microprocessor chips and applications, and as the said major portion of the area is dedicated to SRAM arrays, CMOS SRAM is considered to be the stack holders in the memory market. Because of the scaling feature of CMOS, SRAM had its hold in the market over the past few decades. In recent years, the limitations of the CMOS scaling have raised so many issues like short channel effects, threshold voltage variations. The increased thrust for alternative devices leads to FinFET. FinFET is emerging as one of the suitable alternatives for CMOS and in the region of memory circuits.Design/methodology/approachIn this paper, a new 11 T SRAM cell using FinFET technology has been proposed, the basic component of the cell is the 6 T SRAM cell with 4 NMOS access transistors to improve the stability and also makes it a dual port memory cell. The proposed cell uses a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability thus, helps in reducing the leakage power and active power.FindingsThe cell shows improvement in RSNM (read static noise margin) with LP8T by 2.39× at sub-threshold voltage 2.68× with D6T SRAM cell, 5.5× with TG8T. The WSNM (write static noise margin) and HM (hold margin) of the SRAM cell at 0.9 V is 306 mV and 384 mV. It shows improvement at sub-threshold operation also. The leakage power is reduced by 0.125× with LP8T, 0.022× with D6T SRAM cell, TG8T and SE8T. The impact of process variation on cell stability is also discussed.Research limitations/implicationsThe FinFet has been used in place of CMOS even though the FinFet has been not been a matured technology; therefore, pdk files have been used.Practical implicationsSRAM cell has been designed which has good stability and reduced leakage by which we can make an array and which can be used as SRAM array.Social implicationsThe cell can be used for SRAM memory for low power consumptions.Originality/valueThe work has been done by implementing various leakage techniques to design a stable and improved SRAM cell. The advantage of this work is that the cell has been working for low voltage without degrading the stability factor.

FinFET SRAM cell with improved stability and power for low power applications.

In this paper, a new 11T SRAM cell using Double gate FET (FinFET technology) has been proposed, cell basic component is the 6T SRAM cell with 4 NMOS access transistors to improve the stability over CMOSFET circuits and also makes it a dual port memory cell. The proposed cell also used a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability which helps in reducing the leakage current, active power. The cell shows improvement in RSNM (Read Static Noise Margin) with LP8T by 2.39x at threshold and subthreshold voltage 2.68x with D6T SRAM cell, 5.5x with TG8T. The WSNM (Write Static Noise Margin) and HM (Hold Margin) of the SRAM cell at 0.9V is 306mV and 384mV.At subthreshold operation also, it shows improvement. The Leakage power reduced by 0.125x with LP8T, 0.022x with D6T SRAM cell, TG8T and SE8T. Impact of process variation on cell stability also been analyzed.

Dimensional Quality and Distortion Analysis of Thin-Walled Alloy Parts of AlSi10Mg Manufactured by Selective Laser Melting

The quality and reliability in additive manufacturing is an emerging area. To ensure process quality and reliability, the influence of all process parameters and conditions needs to be understood. The product quality and reliability characteristics, i.e., dimensional accuracy, precision, repeatability, and reproducibility are mostly affected by inherent and systematic manufacturing process variations. This paper presents research on dimensional quality and distortion analysis of AlSi10Mg thin-walled parts developed by a selective laser melting technique. The input process parameters were fixed, and the impact of inherent process variation on dimensional accuracy and precision was studied. The process stability and variability were examined under repeatability and reproducibility conditions. The sample length (horizontal dimension) results revealed a 0.05 mm maximum dimensional error, 0.0197 mm repeatability, and 0.0169 mm reproducibility. Similarly, in sample height (vertical dimension) results, 0.258 mm maximum dimensional error, 0.0237 mm repeatability, and 0.0863 mm reproducibility were observed. The effect of varying design thickness on thickness accuracy was analyzed, and regression analysis performed. The maximum 0.038 mm error and 0.018 mm standard deviation was observed for the 1 mm thickness sample, which significantly decreased for sample thickness ≥2 mm. The % error decreased exponentially with increasing sample thickness. The distortion analysis was performed to explore the effect of sample thickness on part distortion. The 0.5 mm thickness sample shows a very high distortion comparatively, and it is reduced significantly for &gt;0.5 mm thickness samples. The study is further extended to examine the effect of solution heat treatment and artificial aging on the accuracy, precision, and distortion; however, it did not improve the results. Conclusively, the sample dimensions, i.e., length and height, have shown fluctuations due to inherent process characteristics under repeatability and reproducibility conditions. The ANOVA results revealed that sample length means are not statistically significantly different, whereas sample height means are significantly different. The horizontal dimensions in the xy-plane have better accuracy and precision compared to the vertical dimension in the z-axis. The accuracy and precision increased, whereas part distortion decreased with increasing thickness.

A Layout-Based Soft Error Vulnerability Estimation Approach for Combinational Circuits Considering Single Event Multiple Transients (SEMTs)

Radiation-induced single event transients (SETs) are expected to evolve to single event multiple transients (SEMTs) due to the downscaling of transistor feature size, which also increases the difficulty of the vulnerability estimation for large-scale digital integrated circuits. In this paper, a novel layout-based soft error vulnerability estimation approach which is termed LBSEVEA is proposed to evaluate the impact of heavy ions on the vulnerability of combinational circuits. The physical process of interaction between particles and devices, especially nuclear reaction and scattering process are included in the LBSEVEA. In addition, ambipolar diffusion and bipolar amplification effect, which induce additional charge collection of the adjacent transistors and the hitting transistor, are also considered. A new method calculating the collected charge induced by the bipolar amplification effect is presented. By introducing the layout information of the target circuits into the identification of the adjacent cells, SEMTs effect can be considered in the vulnerability estimation. A fast SPICE simulation tool is adopted to conduct the fault injected netlist simulations, which can make a favorable compromise between the consumption of computer resources and simulation precision. Furthermore, induced soft error numbers, distributions of charge collected by the hitting nodes and the adjacent nodes, and SET pulse width distributions are presented. Besides, heatmaps of induced pulse widths for the layout of two benchmark circuits are provided. Finally, the constraints, the flexibility, and the scalability of the LBSEVEA are discussed. The ability to estimate the impact of process variations on the vulnerability is also presented. Compared with simulation and experimental results, the LBSEVEA can fairly estimate the vulnerability of combinational circuits.

Low‐loss inverted taper edge coupler in silicon nitride

An inverted lateral taper with one vertical discrete step was designed for a medium confinement silicon nitride waveguide platform in the C-band, as a chip edge coupler, with a predicted insertion loss of 0.58 dB. The design is supported by an extensive study to evaluate the impact of fabrication process variations on the performance of such a coupler. The device was manufactured and measured, showing an insertion loss of 1.47 dB, which was traced back to fabrication process variations as cross-checked with simulations. To the authors' knowledge, the reported edge coupler is the shortest and among the best performing found for silicon nitride platforms.

Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies

This paper deals with the analysis of the impact of process variations on the detection of resistive short defects, in the context of a logic-based test. Two types of short defects are considered for our investigation, i.e. resistive short to either ground terminal (GND) or power supply terminal (VDD). For both defect types, simple analytical models are proposed that permit to evaluate the robust detectability range in presence of process variations. These models rely on a pre-characterization of the gate library through Monte-Carlo simulation and permit to evaluate the detectability range of a given defect without performing any fault simulation. These models are applied to perform a comparative analysis of 28 nm Bulk and FDSOI (Fully Depleted Silicon-On-Insulator) technologies, considering both regular-VT and low-VT devices. The influence of operating conditions on defect detectability range is also investigated.

Optimization of deep drawing process parameters for cylindrical cup

Abstract This paper is one of the most utilized Metal Forming Process inside the modern field. Distinctive diagnostic, numerical and experimental techniques have been created so as to dissect it. The target of this examination is to decide the variables affecting an illustration procedure and investigating the procedure by fluctuating the Die span, clear thickness, connected power and keeping the Friction as steady. In this paper Punches, clear thickness of same geometry and passes on of different geometries were drawn by utilizing CATIA programming. What's more, an exertion is made to consider the reenactment impact of principle process variation in particular kick the bucket span utilizing limited component investigation. As the FEM code, the financially accessible programming is utilized here. Aluminum composite 6061 is utilized for profound illustration. At long last exhibits an examination of the impact of bite the dust draw sweep, sheet thickness and connected power on the variety in distortion of a profound drawn cup utilizing limited component reproductions. The variety in punch power is limited via doing investigation of difference (ANOVA) for individual components and their cooperations. In this work, the mix of limited component technique and Taguchi plan of investigations and ANOVA has been connected to break down the affecting procedure parameters on Deep illustration for tube shaped cup segment.