Short Channel Effect Immunity Research Articles

Impact of device-to-device interference in nanosheet field-effect transistors

Nanosheet field-effect transistors (NS FETs) are a promising candidate for extremely scaled logic devices beyond FinFETs. The benefits of NS FETs include superior design flexibility and gate controllability, which enable continuous scaling beyond the 3-nm process node, while improving power consumption and performance as well. Recently, many reports have covered how geometrical changes such as the number of stacked nanosheets, inner spacer thickness, and gate stack structures, impact the characteristics of NS FETs. However, few studies have documented the interference effects of multiple NS FETs, even though this is quite important to actual CMOS circuit operation. In this work, we investigated the impact of device-to-device interference on the electrical behavior of adjacent NS FETs using TCAD simulation. We demonstrate that both off-state current (IOFF), and short-channel effects (SCEs) immunity, are significantly affected by adjacent NS FET's on/off operation. Further, we also determined the optimum device structure for maintaining the desired IOFF and SCEs immunity, which can be implemented by adjusting key geometrical parameters, including inner spacer thickness (TSPACER), gate length (LG) and STI collapses (Tcollapse). The superb gate controllability with deeper STI collapses results in much better SCEs properties in terms of IOFF, threshold voltage (VT), and subthreshold swing (SS), providing a promising way of reducing the local variation in NS FETs induced by adjacent devices.

FE/PE/DE gate stack enabling improved analog performance in partially Junction-less NCFETs

Given the short-channel effect immunity of junction-less architectures, further improvement in device performance can be obtained by using a Negative Capacitance based gate stack over such baseline devices. By benchmarking the baseline device, which is a partially Junction-less MOSFET structure, essentially a combination of the Junction-less and Bulk MOSFET device architectures, with experimental data, we then investigate the relative effect of the inclusion of a Ferroelectric (FE) material and Ferroelectric-Paraelectric (FE-PE) stack, respectively, on the existing dielectric (DE) gate stack of the baseline device, resembling a more practical Metal-Ferroelectric-Insulator-Semiconductor (MFIS) NCFET (Negative Capacitance Field Effect Transistor) structure. By ensuring Hysteresis-free transfer characteristics, positive output conductance and Sub-threshold Slope/Threshold Voltage invariability to drain voltage, the FE layer thickness and power supply voltage (maximum drain–source voltage) of the FE-DE and FE-PE-DE gate stacks are determined, which are nearly equivalent capacitively and therefore show similar digital device performance, with the FE-PE-DE gate stack based NCFET showing significantly better analog device performance.

Scallop-shaped p-type FinFETs with improved short-channel effects immunity and driving current

In this work, scallop-shaped p-type fin field-effect transistors (S-FinFETs) that outperform control-FinFETs for a given gate length are fabricated based on a conventional high-к metal gate FinFET fabrication flow. Because of the scallop-shaped gate structure and ultra-thin (∼5 nm) S-fin channel, the S-FinFETs demonstrate a 25% improvement in subthreshold swing and a 54% decrease in drain-induced barrier lowering compared with those of the control-FinFETs for a 20 nm physical gate length. Furthermore, a driving current of 200 μA/μm is obtained for S-FinFETs with a source/drain epitaxial substrate and a gate length of 20 nm, matching the performance of control-FinFETs with a source/drain epitaxial substrate. With improved short-channel effect immunity, the proposed S-FinFET provides a promising candidate beyond-FinFET technology.

Ground plane and selective buried oxide based planar junctionless transistor

AbstractIn this work, we demonstrate a ground plane (GP) based Selective Buried Oxide (SELBOX) Junctionless Transistor (JLT), named as GP-SELBOX-JLT. The use of GP and SELBOX in the proposed device reduces the electric field and enhances volume depletion in the channel, hence improvesION/IOFFratio and scalability. Using calibrated 2-D simulation, we have shown that proposed device exhibits better Short Channel Effect (SHE) immunity as compared to SOI-JLT. Therefore, the proposed GP-SELBOX-JLT can be scaled without degrading the performance in sub 20 nm regime. In addition, the ac study has shown that the cutoff frequency (fT) of GP-SELBOX-JLT is almost equal to conventional SOI-JLT.

Parasitic Capacitance Modeling of Si-Bulk FinFET-Based pMOS

FinFET architecture has witnessed great success at commercial 22-nm node and beyond due to its natural immunity of short-channel effects (SCEs) since the past decade. As the critical size scales down further, the parasitic capacitance becomes a crucial bottleneck to gain the device performance. In this article, analytical parasitic capacitance models (including eight components) are established based on real Si-bulk FinFET pMOS. Compared with the prior works, first, the electric field distribution with a small gate voltage perturbation is employed to reveal the capacitance origin and distribution. Second, except for widely studied parameters (spacer thickness and overlap), the key parameters [source and drain (S/D) recess depth, spacer height, and embedded-SiGe (e-SiGe) cavity overfill] are also studied. The later parameters are seldom considered, but they are widely selected as key in-line monitor items in manufacturing due to their sensitivity to device current and parasitic capacitance. In addition, the geometric dependence on parasitic capacitance is performed and verified well by the 3-D Sentaurus Technology Computer Aided Design (TCAD) simulator. The result shows that the analytical capacitance model can capture geometric behavior well, which finally is understood by the breakdown of the total parasitic capacitance.

TCAD-Based Investigation of Statistical Variability Immunity in U-Channel FDSOI n-MOSFET for Sub-7-nm Technology

In this article, the impact of random fluctuation sources, such as metal gate granularity (MGG), line edge roughness (LER), and random dopant fluctuations (RDFs), are numerically studied for U-shaped n-channel fully depleted silicon on insulator (FDSOI) MOSFET (U-SOIFET) over conventional n-channel FDSOI MOSFET (C-SOIFET) for 7-nm technology node. This article reports that improved short-channel effect immunity in U-SOIFET results in less $1\sigma $ threshold voltage ( ${V}_{T}$ ) and ON-current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) fluctuations compared to C-SOIFET due to MGG and LER variability sources. U-SOIFET exhibits a low ${V}_{T}$ mismatch index ( ${A}_{\Delta VT}=1.78$ mV. $\mu \text{m}$ ) close to the literature reported. Due to combined variability sources, U-SOIFET shows less ${V}_{T}$ , ${I}_{ \mathrm{\scriptscriptstyle ON}}$ , subthreshold swing (SS), and DIBL fluctuations compared to C-SOIFET. Immunity to statistical variability sources makes U-SOIFET a suitable silicon on insulator (SOI) device architecture for future CMOS logic device applications.

Comparative performance analysis of Carbon Nanotube and Si-Nanotube based Field effect Transistors

The continuous scaling of scaling of conventional planar transistors has migrated to nanoscale regime to achieve better performance of the device by mainstream semiconductor industry. To suppress the short channel effects arises in nanoscale devices, many 3D devices and materials have been proposed and investigated. Carbon Nanotube can be used as best materials for replacement of channel material MOSFET transistors due to its good electrical properties. Silicon nanotube field effect transistor is having two gates as an inner and outer gates, provides excellent electrostatic control and short channel effects immunity. In this paper, Carbon Nanotube Field Effect Transistor and Si- Nanotube field effect transistors have been designed and investigated. Performance of CNTFET and Si-NT MOSFET has been analysed and compared. These two field effect transistors may be considered for future of semiconductor industry.

Single and double‐gate based AlGaN/GaN MOS‐HEMTs for the design of low‐noise amplifiers: a comparative study

In this study, a 60 nm gate length double-gate AlGaN/GaN/AlGaN metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT) is proposed and different electrical characteristics, such as DC, small-signal, radio-frequency (RF) and high-frequency noise performances of the devices are characterised through TCAD device simulations. The results of double-gate MOS-HEMT are compared with the TCAD simulation results as well as with available experimental data of single-gate AlGaN/GaN MOS-HEMT having a similar gate length available from the literature. It is observed that the double-gate AlGaN/GaN/AlGaN MOS-HEMT shows good sub-threshold slope, improved ON current, short-channel effect immunity, improved RF and noise performance. A look-up table-based Verilog-A model is developed for both devices and the models are incorporated into the Cadence EDA tool to utilise the proposed device in circuit simulations. The Verilog-A model is applied to design a 1–20 GHz wideband feedback cascode low-noise amplifier (LNA). Performance variability of LNA due to single- and double-gate MOS-HEMT is also investigated.

Intrinsic Voltage Gain of Stacked GAA Nanosheet MOSFETs Operating at High Temperatures

In the semiconductor industry, the scaling down of devices has always been the driver in order to improve circuit area efficiency and high current drive, leading to the triple gate FinFET, which is the newest technology for high performance applications. However, it is believed that these devices cannot reach the sub 7 nm nodes and the GAA nanowires MOSFETs has emerged as one of the most promising candidates for this technology node, as it presents high density of integration and higher electrostatic control between gate and channel (1-2).The studied devices are GAA silicon nanosheet MOSFETs, fabricated at Imec, Leuven – Belgium, with two stacked channels with the vertical distance between the sheets of 7.5 nm, an EOT of 0.9 nm, a width of 15 nm and a channel length varying from 200nm down to 28nm.The threshold voltage (VTH) as a function of temperature is presented in figure 1, in which it is possible to observe that, VTH is reduced (in absolute value) for both n- and pMOS as temperature increases due to the fermi potential reduction. The VTH variation rate for these devices shows to be better when compared to other technologies, presenting a variation around -0.64 mV/ºC for the p-type, and -0.4 mV/ºC for the n-type, while planar fully depleted SOI devices reach around -0.8 mV/ºC (3), junctionless FinFETs can achieve around -0.94 mV/ºC (4) and bulk nFinFETs present values around -0.67 mV/ºC for narrow fins and -0.92 mV/ºC for wide ones (5).It is possible to see that the subthreshold swing (SS) values (figure2) are very close to the theoretical limit for the MOS technology, except for 28nm channel length pMOS devices, indicating that pMOS is more susceptible to short channel effects (SCEs) than the nMOS counterpart.In figure 3, the Drain Induced Barrier Lowering (DIBL) degrades when the temperature increases. DIBL degradation for both n- and pMOS with temperature are very similar, showing a variation rate of 0.11 mV/V.ºC. It is also important to note that although DIBL is affected by the temperature, the obtained values (except for L=28nm) are very small reaching in the worst case 50mV/V at 200ºC.The transconductance (gmsat) and output conductance (gd) on saturation region of n-type and p-type, showed in figure 4, decreases with increased temperature mainly due to the carrier mobility degradation. Although the gd degradation for L=28nm occurs for both caused by the channel length modulation, the p-type device presents a higher degradation in all range of temperature due to the gate to channel electrostatic coupling as already observed in the SS behavior (figure 2).The intrinsic voltage gain (AV) does not change significantly with temperature due to the compensation between the gm degradation and gd improvement as shown in figure 4. Long p-channel devices present higher Av (gm/gd) than n-type GAA FETs due to the smaller values of gd which is not compensated by the gm degradation. However, for short devices the higher gd degradation results in smaller Av. As said before, AV is calculated considering gmsat and gd and both depend on the mobility, so it is possible to note that AV is barely affected by temperature. Other important highlight is the obtained AV values for the studied GAA MOSFETs that are very high considering other multiple gate MOSFET structures. Both nMOS and pMOS nanosheet devices, with channel length of 100 nm, reach around 42 dB and 50dB respectively, while for bulk FinFETs , junctionless SOI nanowires and W-gate SOI nanowires the values achieved are 34 dB (6), 37 dB (7) and 40 dB (8), respectively, for the same VGT and similar channel length.Even though the longest devices show better SCE immunity and higher AV values, the device with a channel length of 28 nm still shows a good performance. The GAA nanosheet achieves AV of 33 dB and 28 dB, for n and p-type, respectively, while triple gate SOI nanowires, with channel length of 40 nm, and W-gate SOI nanowires, with channel length of 20 nm, presents values around 27 dB (9) and 20 dB (10), respectively. Figure 1

Impact of Fin Line Edge Roughness and Metal Gate Granularity on Variability of 10-nm Node SOI n-FinFET

We report the numerical simulation study on the characteristic variability of 10-nm SOI Multi Fin n-FET due to the impact of random fluctuation sources such as gate work function variability induced by metal gate granularity (MGG) and Fin line edge roughness (LER) using quantum corrected 3-D drift diffusion (DD) simulation framework. The statistical simulation predictions reveal that for ultra downscaled SOI FinFET, the MGG predominantly affects device threshold voltage. Similarly, the LER sources are found to strongly influence the variability of device short channel effect immunity and channel mobility of carriers. Both MGG and long correlation length LER are found to strongly influence the overlap and outer fringing parasitic capacitances variability, resulting in increased variability of device intrinsic speed. It is predicted that the presence of combined random fluctuation sources results in the increased variability of threshold mismatch index ( $A_{\text {VT}}$ ) for the sub-10-nm SOI FinFET technology.

Quasi-analytical model-based performance analysis of dual material gate stack strained GAA FinFET

ABSTRACT The evolution of traditional field effect transistor from planar to three-dimensional (3-D) device structure has led to higher package density and high current drive. However, due to continuous scaling, these non-planar devices (FinFET) have been found to suffer from performance degrading short channel effects (SCEs). In this work, a modified field effect device called dual material gate-all-around FinFET with High-K Gate-Oxide stack and strained channel is presented along with its quasi 3-D analytical model to evaluate the SCE immunity. This surface potential-based model includes gate work-function difference, characteristic gate length and equivalent oxide thickness. The channel potential is derived using quasi-3-D scaling equation where the characteristic length is derived using equivalent number of gates model. With the simple expression of potential distribution, threshold voltage and subthreshold swing have been obtained using minimum central potential. The device immunity to SCEs such as drain-induced barrier lowering, hot carriers and subthreshold degradation has also been examined for various structural and material modifications. The proposed analytical model has been verified using the 3-D numerical device simulator ATLAS.

An analytical drain current model for cylindrical gate DMG-GC-DOT MOSFET

ABSTRACTAn analytical model of dual-material gate graded channel and dual oxide thickness cylindrical gate (DMG-GC-DOT) MOSFET is investigated in this work. Analytical model of drain current is developed using a quasi-two-dimensional cylindrical form of the Poisson equation and is expressed as a function of the surface potential, which is determined using the expressions of the current density. The device DMG-GC-DOT is compared with other structures such as DMG and DMG-DOT and demonstrates that our structure offers better immunity of short channel effects (incorporated in drain current model). The results obtained analytically are in agreement with those obtained by using the Silvaco Atlas-TCAD software.

Ambient Temperature-Induced Device Self-Heating Effects on Multi-Fin Si n-FinFET Performance

Device self-heating effects (SHEs) in nonplanar Si MOS transistors such as fin field-effect transistors (FinFETs) and nanowire FETs have become a serious issue in designing well-tempered CMOS devices for future logic nodes. The device thermal contact resistances are strongly influenced by both the ambient temperature and within device lattice temperature. The ambient heat energy coupling through the thermal contact resistances will strongly impact device SHE in FinFETs due to increase in the surface-to-volume ratio of confined geometry thin Si Fin. In this paper, we report a 3-D quantum-corrected electrothermal numerical device analysis involving a coupled hydrodynamic and thermodynamic transport models for a target Si 3-Fin bulk n-FinFET. The numerical device simulations quantitatively predicted the impact of ambient and electrical contact temperatures on device short-channel effect immunity and performance. The simulation parameters are calibrated with the state-of-the-art Si FinFET measurement data from the literature. Our numerical simulation findings establish the phenomena of ambient temperature-induced device SHE on Si n-FinFETs performance for sub-14-nm technology nodes. The simulation predictions establish the fact that the thermal contact resistances and the within-chip ambient temperature ( ${T}_{A}$ ) have adverse effects on device lumped thermal resistance ( ${R}_{\text {th,eff}}$ ) and performance metrics. Finally, we have numerically analyzed the FinFET design solutions (tapered source and drain regions) to improve the tolerance against the ambient temperature-induced SHE.

Novel GAA Si Nanowire p-MOSFETs With Excellent Short-Channel Effect Immunity via an Advanced Forming Process

In this letter, Gate-All-Around (GAA) nanowire (NW) p-MOSFETs with new approaches to fabricate totally isolated channels in replacement metal gate (RMG) are reported for the first time. Few reformed fin forming processes based on conventional high- k /metal gate FinFET flow are implemented to fabricate the GAA devices. Two profiles of NW channels, such as circular and inverted droplet, were fabricated by H2 baking and oxidation methods in the RMG process. The proposed methods would increase the process thermal budget and improve film quality for the NW channels. Providing both structural and process advantages, the optimized devices with $L_{g} = 16$ nm demonstrate superb short-channel effect (SCE) immunity characteristics, with SS = 61.86$ mV/dec and DIBL = 6.5 mV/V for the inverted droplet NW device; these results are very close to the ideal limits of MOSFETs. The results also indicate that the inverted droplet NW devices have a slightly better SCE control than the circular NWs of similar geometric size.

Investigation and analysis of dual-k spacer with different materials and spacer lengths for nanowire-FET performance

In this work, dual-k spacer structures are investigated using a variety of materials along the high-k spacer length in detail. It is known that not only the higher permittivity materials of high-k spacer boost the on-current but also lower permittivity materials of low-k spacer effectively reduce the off-current. By compared the results of other various single spacers and dual-k spacers, it is HfO2/Vacuum dual-k spacer that shows relatively higher ION, ION/IOFF, better immunity of short channel effects and outstanding device performances.

Plasma-Induced Interfacial Layer Impacts on TFETs With Poly-Si Channel Film by Oxygen Plasma Surface Treatment

In this paper, tunnel field-effect transistor (TFETs) with polycrystalline-silicon (poly-Si) channel film has been demonstrated to exhibit better short-channel effects (SCEs) immunity than conventional poly-Si thin-film transistors. Oxygen (O2) plasma surface treatment before the deposition of gate dielectric can produce a plasma-induced interfacial layer, which can passivate the interface trap state density ~25%. In addition, the ON-state transconductance $G_{m}$ is improved ~54% due to the decrease of tunneling distance of band-to-band tunneling. However, the $G_{m}$ improvement of poly-Si TFETs is decreased with the scaling down of channel length due to the less trap state density in the small area of poly-Si channel film. Moreover, the O2 plasma surface treatment can also reduce the grain boundary trap state density of poly-Si channel film ~37%, which can reduce the trap-assisted tunneling current of poly-Si TFETs to suppress the length dependence of drain leakage current in the subthreshold region. Consequently, the O2 plasma surface treatment can not only improve the ON-state current and OFF-state leakage current of poly-Si TFETs, but also further improve the SCEs of poly-Si TFETs.

Performance improvement of poly-Si tunnel thin-film transistor by NH3 plasma treatment

In this paper, low-temperature polycrystalline silicon (poly-Si) tunnel thin-film transistors (tunnel-TFTs) are demonstrated to show excellent short-channel effects immunity due to their special current transport mechanism: inter-band tunneling. The ammonia (NH3) plasma surface treatment before the deposition of gate dielectric can significantly reduce the grain boundary trap state densities (NGB) of poly-Si channel film and the interface trap state densities (Nit) at the gate-oxide/poly-Si interface. About 27% reduction of NGB by NH3 plasma surface treatment can reduce the minimum drain current ~0.51× and improve the subthreshold slope due to the suppression of trap-assisted tunneling, which dominates the current transport in the subthreshold operation region. In addition, about 37% reduction of Nit by NH3 plasma surface treatment can significantly enhance the on-state current ~2.86× due to the increase of band bending of poly-Si channel potential, which can decrease the tunneling distance to increase the electron tunneling probability. Consequently, the performance improvement of poly-Si tunnel-TFTs by the NH3 plasma surface treatment would be helpful for the development of system-on-panel and three-dimension integrated circuits.

Performance Improvement of Poly-Si Tunnel FETs by Trap Density Reduction

In this brief, the tunnel FETs (TFETs) with a polycrystalline-Si (poly-Si) channel have been demonstrated, and the performance of the poly-Si TFET shows a significant improvement by the reduction of interface trap states ( $N_{\mathrm {{it}}}$ ) near the conduction band edge. The ON-state current ( $I_{\mathrm{\scriptscriptstyle ON}}$ ) conduction mechanism, band-to-band tunneling, of poly-Si TFETs is strongly affected by the band bending of poly-Si channel. The N2 plasma surface treatment before the gate dielectric deposition can produce a plasma-induced interfacial layer to reduce $N_{\mathrm {it}}$ obviously, which greatly enhances the surface potential modulation by the gate and improves the $I_{\mathrm{\scriptscriptstyle ON}}$ value of poly-Si TFETs $\sim 3.7\times $ . The OFF-state current ( $I_{\mathrm { {min}}}$ ) attributed to the trap-assisted tunneling (TAT) can also be reduced by a factor of $\sim 40$ %, because of the passivation of grain boundary trap ( $N_{\mathrm {trap}}$ ) of the poly-Si channel film. Consequently, the ON/OFF current ratio is enhanced from $9.42\times 10^{5}$ to $6.13\times 10^{6}$ . In addition, the subthreshold swing, $I_{{\mathrm{\scriptscriptstyle ON}}}$ , and $I_{\mathrm { {min}}}$ of poly-Si TFET exhibit superior short-channel effect immunity, which shows good feasibility for implementing high packing density of poly-Si thin-film transistors, such as 3-D nonvolatile memory and pixel driving device.

Device parameter optimization for sub-20 nm node HK/MG-last bulk FinFETs**Project supported by the National 02 IC Projects and the Opening Project of Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences.

Sub-20 nm node bulk FinFET PMOS devices with an all-last high-k/metal gate (HK/MG) process are fabricated and the influence of a series of device parameters on the device scaling is investigated. The high and thin Fin structure with a tapered sidewall shows better performance than the normal Fin structure. The punch through stop layer (PTSL) and source drain extension (SDE) doping profiles are carefully optimized. The device without SDE annealing shows a larger drive current than that with SDE annealing due to better Si crystal regrowth in the amorphous Fin structure after source/drain implantation. The band-edged MG has a better short channel effect immunity, but the lower effective work function (EWF) MG shows a larger driveability. A tradeoff choice for different EWF MGs should be carefully designed for the device's scaling.

Self-Aligned Fin-On-Oxide (FOO) FinFETs for Improved SCE Immunity and Multi-VTH Operation on Si Substrate

The paper proposed a simple and novel approach to fabricate Fin-On-Oxide (FOO) FinFETs on silicon (Si) substrates for improved electrical characteristics in scaled devices. Based on conventional bulk-Si FinFET integration flow, a special step of a fin notch etching is performed, followed by a process of liner oxidation and isolation-oxide filling and recess. The fin above the notch is physically isolated from the substrate and turns into a self-aligned FOO structure. The fabricated p-type FOO FinFETs have demonstrated excellent short-channel effect (SCE) characteristics with subthreshold slope (SS) of 69 mV/dec and drain-induced barrier lowering (DIBL) of 22 mV/V for a physical gate length (LG) of 27 nm. For 14 nm devices, SS of 86 mV/dec and DIBL of 106 mV/V have been achieved, which are much better than those of the bulk-silicon FinFET counterpart with similar process. Meanwhile, the steady threshold voltage (VTH) shifting by the substrate biasing is realized in the FOO FinFET without performance degradations. The linearity of the VTH on the bias voltage is −6 mV/V. The self-aligned FOO-FinFET with a simple process provides a promising method to improve the SCE immunity as well as provides the multi-VTH operation for the scaled FinFET on Si substrates for future ultra-low power circuit applications. © The Author(s) 2015. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution 4.0 License (CC BY, http://creativecommons.org/licenses/by/4.0/), which permits unrestricted reuse of the work in any medium, provided the original work is properly cited. [DOI: 10.1149/2.0071504ssl] All rights reserved.