Impact of device-to-device interference in nanosheet field-effect transistors

Abstract

Nanosheet field-effect transistors (NS FETs) are a promising candidate for extremely scaled logic devices beyond FinFETs. The benefits of NS FETs include superior design flexibility and gate controllability, which enable continuous scaling beyond the 3-nm process node, while improving power consumption and performance as well. Recently, many reports have covered how geometrical changes such as the number of stacked nanosheets, inner spacer thickness, and gate stack structures, impact the characteristics of NS FETs. However, few studies have documented the interference effects of multiple NS FETs, even though this is quite important to actual CMOS circuit operation. In this work, we investigated the impact of device-to-device interference on the electrical behavior of adjacent NS FETs using TCAD simulation. We demonstrate that both off-state current (IOFF), and short-channel effects (SCEs) immunity, are significantly affected by adjacent NS FET's on/off operation. Further, we also determined the optimum device structure for maintaining the desired IOFF and SCEs immunity, which can be implemented by adjusting key geometrical parameters, including inner spacer thickness (TSPACER), gate length (LG) and STI collapses (Tcollapse). The superb gate controllability with deeper STI collapses results in much better SCEs properties in terms of IOFF, threshold voltage (VT), and subthreshold swing (SS), providing a promising way of reducing the local variation in NS FETs induced by adjacent devices.